Abstract: A serial data receiver is disclosed. In one embodiment, a receiver includes an amplifier circuit configured to receive one or more signals that encode a serial data stream that includes a plurality of data symbols and to perform a comparison of the one or more signals to a threshold value to generate a recovered data symbol. The receiver circuit further includes a threshold circuit configured to generate a delayed version of the one or more signals. The threshold circuit is further configured to generate a delayed data symbol using the delayed version of the one or more signals and adjust the threshold value using the delayed data symbol.

Abstract: An apparatus includes first and second receiver circuits and a decision circuit. The first receiver circuit is configured to generate a first data symbol from a particular input data symbol of a plurality of input data symbols included in an input signal. The second receiver circuit is configured to generate a second data symbol from the particular input data symbol. The decision circuit is configured to select, using respective values of one or more previous output data symbols, either the first or second data symbol as a current output data symbol. In response to a change in value between successive input data symbols, the first and second receiver circuits are configured to generate the first and second data symbols with respective data valid windows with different durations.

Abstract: An apparatus includes first and second receiver circuits and a decision circuit. The first receiver circuit is configured to generate a first data symbol from a particular input data symbol of a plurality of input data symbols included in an input signal. The second receiver circuit is configured to generate a second data symbol from the particular input data symbol. The decision circuit is configured to select, using respective values of one or more previous output data symbols, either the first or second data symbol as a current output data symbol. In response to a change in value between successive input data symbols, the first and second receiver circuits are configured to generate the first and second data symbols with respective data valid windows with different durations.

Abstract: An apparatus includes first and second receiver circuits and a decision circuit. The first receiver circuit is configured to generate a first data symbol from a particular input data symbol of a plurality of input data symbols included in an input signal. The second receiver circuit is configured to generate a second data symbol from the particular input data symbol. The decision circuit is configured to select, using respective values of one or more previous output data symbols, either the first or second data symbol as a current output data symbol. In response to a change in value between successive input data symbols, the first and second receiver circuits are configured to generate the first and second data symbols with respective data valid windows with different durations.

Abstract: A level shifter circuit is disclosed. A level shifter circuit includes a static pull-down circuit that causes an output node to be pulled low responsive to an input circuit receiving a first logic value on an input node. The input node is coupled to receive a signal from circuitry in a first voltage domain, while the output node is configured to provide a corresponding signal into a second voltage domain. The static pull-down circuit is implemented with a passgate having a pair of transistors coupled in series. The level shifter circuit further includes a dynamic pull-up circuit that, when active, causes the output node to be pulled high responsive to the input circuit receiving a second logic value on the input node. The dynamic pull-up circuit includes third and fourth transistors coupled in series between the output node and a supply voltage node of the second voltage domain.