Patents by Inventor Mitesh Goyal
Mitesh Goyal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11569799Abstract: A True Single-Phase Clock (TSPC) NAND-based reset flip-flop includes a reset functionality to perform a reset operation. The flip-flop with the reset functionality includes a master section and a slave section. The reset functionality is achieved using two transistors in the master section. The master section and the slave section operate using the TSPC. The master section and the slave section may include a plurality of NAND circuits and a NAND and NOR circuit for performing the reset operation. The master section outputs a plurality of internal signals on receiving a data input, a scan enable signal, a scan input signal, a reset control signal, and a clock signal. The slave section generates an output on receiving the plurality of internal signals received from the master section.Type: GrantFiled: March 1, 2021Date of Patent: January 31, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Aroma Bhat, Arani Roy, Mitesh Goyal, Abhishek Ghosh
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Patent number: 11366161Abstract: A True Single Phase Clock (TSPC) pre-charge based flip-flop is provided. The flip-flop includes a scan section, a master section, and a slave section. The scan section receives a scan enable signal, a scan input signal, a clock signal, and feedback data from the master section, and outputs an internal signal to the master section based on the scan enable signal, the scan input signal, the clock signal, and the feedback data. The master section is coupled to the scan section and receives the internal signal and a data input, and outputs a master feedback signal to the slave section based on the internal signal, the data input, and the feedback data. The slave section is coupled to the master section and generates an output by latching the master feedback signal received from the master section according to the clock signal. The clock signal is a True-Single-Phase-Clock (TSPC).Type: GrantFiled: December 10, 2020Date of Patent: June 21, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Arani Roy, Arava Prakash, Aroma Bhat, Mitesh Goyal, Abhishek Ghosh
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Patent number: 11362648Abstract: A pre-discharging based flip-flop having a negative setup time can include a flip-flop with an inverted output QN. The flip-flop includes a master section and a slave section. The master section latches a data input or a scan input signal based on a scan enable signal, and the slave section retains a previous value of the inverted output QN when a clock signal is at a low logic level. The master section retains a previously latched value of the data input or the scan input signal and the slave section fetches the latched value of the master section and provides a new inverted output QN when the clock signal is at a high logic level. Further, the master section includes sub-sections that are operated using a negative clock signal. An output of the master section is discharged to zero for a half of a phase of the clock cycle.Type: GrantFiled: December 10, 2020Date of Patent: June 14, 2022Inventors: Aroma Bhat, Abdur Rakheeb, Arani Roy, Mitesh Goyal, Abhishek Ghosh
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Publication number: 20220173725Abstract: A True Single-Phase Clock (TSPC) NAND-based reset flip-flop includes a reset functionality to perform a reset operation. The flip-flop with the reset functionality includes a master section and a slave section. The reset functionality is achieved using two transistors in the master section. The master section and the slave section operate using the TSPC. The master section and the slave section may include a plurality of NAND circuits and a NAND and NOR circuit for performing the reset operation. The master section outputs a plurality of internal signals on receiving a data input, a scan enable signal, a scan input signal, a reset control signal, and a clock signal. The slave section generates an output on receiving the plurality of internal signals received from the master section.Type: ApplicationFiled: March 1, 2021Publication date: June 2, 2022Inventors: AROMA BHAT, Arani Roy, Mitesh Goyal, Abhishek Ghosh
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Publication number: 20210184660Abstract: A pre-discharging based flip-flop having a negative setup time can include a flip-flop with an inverted output QN. The flip-flop includes a master section and a slave section. The master section latches a data input or a scan input signal based on a scan enable signal, and the slave section retains a previous value of the inverted output QN when a clock signal is at a low logic level. The master section retains a previously latched value of the data input or the scan input signal and the slave section fetches the latched value of the master section and provides a new inverted output QN when the clock signal is at a high logic level. Further, the master section includes sub-sections that are operated using a negative clock signal. An output of the master section is discharged to zero for a half of a phase of the clock cycle.Type: ApplicationFiled: December 10, 2020Publication date: June 17, 2021Inventors: Aroma Bhat, Abdur Rakheeb, Arani Roy, Mitesh Goyal, Abhishek Ghosh
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Publication number: 20210173006Abstract: A True Single Phase Clock (TSPC) pre-charge based flip-flop is provided. The flip-flop includes a scan section, a master section, and a slave section. The scan section receives a scan enable signal, a scan input signal, a clock signal, and feedback data from the master section, and outputs an internal signal to the master section based on the scan enable signal, the scan input signal, the clock signal, and the feedback data. The master section is coupled to the scan section and receives the internal signal and a data input, and outputs a master feedback signal to the slave section based on the internal signal, the data input, and the feedback data. The slave section is coupled to the master section and generates an output by latching the master feedback signal received from the master section according to the clock signal. The clock signal is a True-Single-Phase-Clock (TSPC).Type: ApplicationFiled: December 10, 2020Publication date: June 10, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Arani Roy, Arava Prakash, Aroma Bhat, Mitesh Goyal, Abhishek Ghosh
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Patent number: 10996709Abstract: A clock gate circuit (CGC) is described that optimizes dynamic power of the CGC when clock is gated. The CGC helps in dynamic power reduction of clock network by offering lower clock pin capacitance and also by providing clock pin driver downsizing opportunities. Switching power, and hence, dynamic power is reduced when load on the input clock pin is reduced. Further, dynamic power of the clock network also reduces by downsizing the clock buffers, which drive the CGC clock pins.Type: GrantFiled: August 30, 2019Date of Patent: May 4, 2021Assignee: Intel CorporationInventors: Gururaj Shamanna, Mitesh Goyal, Jagadeesh Chandra Salaka, Purna C. Nayak, Abhishek Sharma, Harishankar Sahu
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Publication number: 20210064076Abstract: A clock gate circuit (CGC) is described that optimizes dynamic power of the CGC when clock is gated. The CGC helps in dynamic power reduction of clock network by offering lower clock pin capacitance and also by providing clock pin driver downsizing opportunities. Switching power, and hence, dynamic power is reduced when load on the input clock pin is reduced. Further, dynamic power of the clock network also reduces by downsizing the clock buffers, which drive the CGC clock pins.Type: ApplicationFiled: August 30, 2019Publication date: March 4, 2021Inventors: Gururaj Shamanna, Mitesh Goyal, Jagadeesh Salaka, Purna C. Nayak, Abhishek Sharma, Harishankar Sahu
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Patent number: 8963210Abstract: An integrated circuit (IC) cell may include first and second semiconductor regions, and parallel electrically conductive lines extending above the first and second semiconductor regions. The IC cell may further include electrically conductive line contacts electrically connected to the parallel electrically conductive lines, and may include at least one first line contact between the first semiconductor region and a corresponding end of the IC cell, and at least one second line contact between the first semiconductor region and the second semiconductor region. Adjacent ones of the electrically conductive lines may be respectively coupled to one of the at least one first line contact and to one of the at least one second line contact.Type: GrantFiled: September 21, 2011Date of Patent: February 24, 2015Assignees: STMicroelectronics SA, STMicroelectronics, Inc.Inventors: Rwik Sengupta, Rohit Kumar Gupta, Mitesh Goyal, Olivier Menut
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Publication number: 20120132963Abstract: An integrated circuit (IC) cell may include first and second semiconductor regions, and parallel electrically conductive lines extending above the first and second semiconductor regions. The IC cell may further include electrically conductive line contacts electrically connected to the parallel electrically conductive lines, and may include at least one first line contact between the first semiconductor region and a corresponding end of the IC cell, and at least one second line contact between the first semiconductor region and the second semiconductor region. Adjacent ones of the electrically conductive lines may be respectively coupled to one of the at least one first line contact and to one of the at least one second line contact.Type: ApplicationFiled: September 21, 2011Publication date: May 31, 2012Applicants: STMicroelectronics STM, STMicroelectronics (Grenoble 2) SAInventors: Rwik Sengupta, Rohit Kumar Gupta, Mitesh Goyal, Olivier Menut