Patents by Inventor Mitesh Patel

Mitesh Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7291548
    Abstract: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: November 6, 2007
    Assignee: Intel Corporation
    Inventors: Daewoong Suh, Saikumar Jayaraman, Stephen E. Lehman, Mitesh Patel, Tiffany A. Byrne, Edward L. Martin, Mohd Erwan B. Basiron, Wei Keat Loh, Sheau Hooi Lim, Yoong Tatt P. Chin
  • Publication number: 20070190772
    Abstract: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.
    Type: Application
    Filed: April 17, 2007
    Publication date: August 16, 2007
    Inventors: Daewoong Suh, Saikumar Jayaraman, Stephen Lehman, Mitesh Patel, Tiffany Byrne, Eward Martin, Mohd Erwan Basiron, Wei Loh, Sheau Lim, Yoong Tatt Chin
  • Patent number: 7253088
    Abstract: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: August 7, 2007
    Assignee: Intel Corporation
    Inventors: Daewoong Suh, Saikumar Jayaraman, Stephen E. Lehman, Mitesh Patel, Tiffany A. Byrne, Edward L. Martin, Mohd Erwan B. Basiron, Wei Keat Loh, Sheau Hooi Lim, Yoong Tatt P. Chin
  • Publication number: 20070158823
    Abstract: A chip package includes a thermal interface material disposed between a die backside and a heat sink. The thermal interface material includes a first metal particle that is covered by a dielectric film. The dielectric film is selected from an inorganic compound of the first metal or an inorganic compound coating of a second metal. The dielectric film diminishes overall heat transfer from the first metal particle in the thermal interface material by a small fraction of total possible heat transfer without the dielectric film. A method of operating the chip includes biasing the chip with the dielectric film in place.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 12, 2007
    Inventors: Ashay Dani, Anna Prakash, Saikumar Jayaraman, Mitesh Patel, Vijay Wakharkar
  • Publication number: 20070152325
    Abstract: A chip package includes a thermal interface material disposed between a die backside and a heat sink. A dielectric sheet is also disposed between the die backside and the heat sink. The dielectric sheet diminishes overall heat transfer from the die to the heat sink by a small fraction of total possible heat transfer without the dielectric sheet. A method of operating the chip includes biasing the chip with the dielectric sheet in place.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 5, 2007
    Inventors: Ashay Dani, Anna Prakash, Saikumar Jayaraman, Mitesh Patel, Vijay Wakharkar
  • Publication number: 20060219715
    Abstract: A system and method is provided in which a radio frequency transmitter and/or a microwave frequency transmitter applies radio and/or microwave frequency energy, respectively, to an imprinted material to cure the imprinted material. In some embodiments, an oven may be used to apply thermal energy to the imprinted material in conjunction with the radio and/or microwave frequency energy to cure the imprinted material. In other embodiments, an oven is not used. The imprinted material may also include a susceptor that absorbs radio and/or microwave frequency energy and responsive thereto emits thermal energy to aid in curing the imprinted material. Further, at least one susceptor may be located externally and adjacent to the imprinted material. The external susceptor may absorb radio and/or microwave frequency energy, respectively, and responsive thereto emits thermal energy towards the imprinted material to aid in curing the imprinted material.
    Type: Application
    Filed: June 7, 2006
    Publication date: October 5, 2006
    Inventors: Shalabh Tandon, Mitesh Patel
  • Publication number: 20060068579
    Abstract: A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a low melting-point solder bump that is disposed upon the lower surface. The stress-relief layer flows against the low melting-point solder bump. A stress-compensation collar is formed on a board to which the substrate is mated, and the stress-compensation collar partially embeds the low melting-point solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes the low melting-point solder, the stress-relief layer, and the stress-compensation collar is also included.
    Type: Application
    Filed: September 29, 2004
    Publication date: March 30, 2006
    Inventors: Daewoong Suh, Saikumar Jayaraman, Stephen Lehman, Mitesh Patel, Tiffany Byrne, Edward Martin, Mohd Erwan Basiron, Wei Keat Loh, Sheau Hooi Lim, Yoong Tatt Chin
  • Publication number: 20060065984
    Abstract: Numerous embodiments of an apparatus and method to stress and warpage of semiconductor packages are described. In one embodiment, a semiconductor die is disposed above a substrate. An encapsulating material is disposed above the substrate and semiconductor die, in which the encapsulating material has a combination of a low coefficient of thermal expansion material and a high coefficient of thermal expansion material.
    Type: Application
    Filed: November 18, 2005
    Publication date: March 30, 2006
    Inventors: James Matayabas, Gudbjorg Oskarsdottir, Mitesh Patel
  • Publication number: 20060011616
    Abstract: A system and method is provided in which a radio frequency transmitter and/or a microwave frequency transmitter applies radio and/or microwave frequency energy, respectively, to an imprinted material to cure the imprinted material. In some embodiments, an oven may be used to apply thermal energy to the imprinted material in conjunction with the radio and/or microwave frequency energy to cure the imprinted material. In other embodiments, an oven is not used. The imprinted material may also include a susceptor that absorbs radio and/or microwave frequency energy and responsive thereto emits thermal energy to aid in curing the imprinted material. Further, at least one susceptor may be located externally and adjacent to the imprinted material. The external susceptor may absorb radio and/or microwave frequency energy, respectively, and responsive thereto emits thermal energy towards the imprinted material to aid in curing the imprinted material.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 19, 2006
    Inventors: Shalabh Tandon, Mitesh Patel
  • Publication number: 20060001158
    Abstract: Numerous embodiments of an apparatus and method to stress and warpage of semiconductor packages are described. In one embodiment, a semiconductor die is disposed above a substrate. An encapsulating material is disposed above the substrate and semiconductor die, in which the encapsulating material has a combination of a low coefficient of thermal expansion material and a high coefficient of thermal expansion material.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: James Matayabas, Gudbjorg Oskarsdottir, Mitesh Patel