Patents by Inventor Mithun Gopal V V

Mithun Gopal V V has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PRINTED CIRCUIT BOARD HAVING A DIFFERENTIAL PAIR ROUTING TOPOLOGY WITH NEGATIVE PLANE ROUTING AND IMPEDANCE CORRECTION STRUCTURES
    Publication number: 20230209726
    Abstract: A printed circuit board including a set of five layers encompassing a breakout area is described. The set includes a first ground layer, a first signal layer having a first conductive layer within the breakout area, a second ground layer having conductive material, a second signal layer having a second conductive layer within the breakout area, and a third ground layer. The second ground layer having a void forming a differential pair being two parallel traces, and being separated into a first portion positioned within the breakout area and a second portion outside of the breakout area. The differential pair having a first width and a first spacing within the breakout area and a second width and second spacing outside of the breakout area, with the second width greater than the first width. The first and second conductive layers forming a first ground plane and a second ground plane.
    Type: Application
    Filed: December 24, 2021
    Publication date: June 29, 2023
    Inventors: Aneesh Kachroo, Mithun Gopal V V, Navneeth Jayaraj
  • Printed circuit board having a differential pair routing topology with negative plane routing and impedance correction structures
    Patent number: 11234325
    Abstract: A printed circuit board including a set of five layers encompassing a breakout area is described. The set includes a first ground layer, a first signal layer having a first conductive layer within the breakout area, a second ground layer having conductive material, a second signal layer having a second conductive layer within the breakout area, and a third ground layer. The second ground layer having a void forming a differential pair being two parallel traces, and being separated into a first portion positioned within the breakout area and a second portion outside of the breakout area. The differential pair having a first width and a first spacing within the breakout area and a second width and second spacing outside of the breakout area, with the second width greater than the first width. The first and second conductive layers forming a first ground plane and a second ground plane.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: January 25, 2022
    Assignee: Infinera Corporation
    Inventors: Aneesh Kachroo, Mithun Gopal V V, Navneeth Jayaraj
  • PRINTED CIRCUIT BOARD HAVING A DIFFERENTIAL PAIR ROUTING TOPOLOGY WITH NEGATIVE PLANE ROUTING AND IMPEDANCE CORRECTION STRUCTURES
    Publication number: 20200404774
    Abstract: A printed circuit board including a set of five layers encompassing a breakout area is described. The set includes a first ground layer, a first signal layer having a first conductive layer within the breakout area, a second ground layer having conductive material, a second signal layer having a second conductive layer within the breakout area, and a third ground layer. The second ground layer having a void forming a differential pair being two parallel traces, and being separated into a first portion positioned within the breakout area and a second portion outside of the breakout area. The differential pair having a first width and a first spacing within the breakout area and a second width and second spacing outside of the breakout area, with the second width greater than the first width. The first and second conductive layers forming a first ground plane and a second ground plane.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Inventors: Aneesh Kachroo, Mithun Gopal V V, Navneeth Jayaraj