Patents by Inventor Mithun Kumar

Mithun Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12137136
    Abstract: A cloud-based, integrated business application suite includes an add-in that enables access from a client device to a first server, but not a second server. A user accesses the first server through an interface of the integrated suite to request a webpage which launches a first local instance of a service application. The first local instance of the service application sets up a local storage location and provides this location to a URL that is used to launch a webpage that is a client of the second server. A second local instance of the service application which is aware of the storage location is launched and this instance stores data requested from the second server in the identified local storage location. The stored information is read from the storage location by the first instance of the service application and is provided to the integrated application suite.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: November 5, 2024
    Assignee: OPEN TEXT SA ULC
    Inventors: Pardeep Kumar, Mithun Karkada Sathisha, Divisha Nikunj Varandani, Prashantha Hanumanthappa, Panchakshrappa Pramod, Navaid Alam
  • Publication number: 20240355363
    Abstract: Methods, systems, and devices for a bit line contact scheme in a memory system stack are described. A memory architecture may include bit lines coupled with bit line contacts, and pillars coupled with circuitry associated with supporting operation of the bit lines. Hybrid plugs may be integrated into the pillars to couple the bit line contacts with the pillars, forming a conductive path between the bit lines and the circuitry. The hybrid plugs may be recessed within the pillars such that the hybrid plugs do not extend through the memory architecture beyond the pillars. The hybrid plugs may include one or more relatively low capacitance, conductive materials, such as a titanium alloy material (e.g., titanium, titanium nitride), a tungsten alloy material (e.g., tungsten, tungsten nitride), or any combination thereof, among other materials.
    Type: Application
    Filed: April 9, 2024
    Publication date: October 24, 2024
    Inventors: Mithun Kumar Ramasahayam, Indra V. Chary, Meng-Wei Kuo
  • Publication number: 20240256629
    Abstract: Data processing systems and methods, according to various embodiments, are adapted for determining a categorization for each tracking tool that executes on a particular webpage based on a variety of criteria, such as the purpose of the tracking tool and its source script. The system may compare the characteristics of tracking tools on a webpage to a database of known tracking tools to determine the appropriate categorization. When a user visits the webpage, the system analyzes these categories and determines whether the tracking tool should be permitted to run based on the categories and/or other criteria, such as whether the user has consented to the use of that type of tracking tool.
    Type: Application
    Filed: March 13, 2024
    Publication date: August 1, 2024
    Applicant: OneTrust, LLC
    Inventors: Patrick Whitney, Kevin Jones, Brian Kelly, Subramanian Viswanathan, Casey Hill, Jeffrey Baucom, Madhusudhan Kunhambu, Mithun Babu, Rajneesh Kesavan, Santosh Kumar Koti, Sathish Gopalakrishnan, Anand Balasubramanian, Mohamed Kabad, Jayamohan Puthenveetil, Jonathan Blake Brannon
  • Publication number: 20240242378
    Abstract: The disclosure provides a computer implemented method for detecting an output pose of interest of a subject in real-time, the method comprising recording an image frame of the subject using an imaging device, determining an output pose of interest by processing the image frame using a machine learning model that comprises a rule-based pose inference model and a data-driven pose inference model wherein with the data-driven pose inference model, determining a data-driven pose of interest by processing a single frame of the subject, and wherein with the rule-based pose inference model, determining a rule-based output pose of interest by processing the same single image frame, and determining as the output pose of interest the rule-based output pose of interest, if the rule-based pose inference model is able to determine the rule-based output pose of interest, otherwise determining the data-driven pose of interest as the output pose of interest.
    Type: Application
    Filed: May 6, 2022
    Publication date: July 18, 2024
    Applicant: Continental Automotive Technologies GmbH
    Inventors: Lei Li, Mithun Das, Matthias Horst Meier, Sunil Kumar Thakur
  • Patent number: 11948259
    Abstract: Embodiments of the present invention provide a system for processing and integrating real-time environment instances into virtual reality live streams. The system is configured for determining that a user is accessing a virtual environment, capturing real-time environment instance associated with the virtual environment via one or more capturing devices, creating a neutral environment template based on processing the real-time environment instance, embedding one or more preferential objects associated with the user into the neutral environment template to generate a preferred environment template, and instantaneously integrating the preferred environment template into a virtual reality live stream associated with the virtual environment in real-time.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: April 2, 2024
    Assignee: BANK OF AMERICA CORPORATION
    Inventors: Suryanarayan Parthasarathi Chakravarthi, Pritika Bhatia, Harshit Bhatt, Saisrikanth Chitty, Neha Jain, Mithun Kumar, Madhumitha Swaminathan Rangarajan
  • Publication number: 20240071505
    Abstract: Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.
    Type: Application
    Filed: August 24, 2023
    Publication date: February 29, 2024
    Inventors: Jiewei Chen, Mithun Kumar Ramasahayam, Tomoko Ogura Iwasaki, June Lee, Luyen Vu
  • Publication number: 20240071430
    Abstract: A system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars and forms a logic layer disposed above the memory array, the logic layer comprising a plurality of latches arranged along a plurality of logic layer latch pillars, the plurality of latches to store a multi-bit data pattern representing a sequence of bits to be programmed to the plurality of memory cells of the memory array.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Jiewei Chen, Mithun Kumar Ramasahayam, Tomoko Ogura Iwasaki
  • Publication number: 20240062477
    Abstract: Embodiments of the present invention provide a system for processing and integrating real-time environment instances into virtual reality live streams. The system is configured for determining that a user is accessing a virtual environment, capturing real-time environment instance associated with the virtual environment via one or more capturing devices, creating a neutral environment template based on processing the real-time environment instance, embedding one or more preferential objects associated with the user into the neutral environment template to generate a preferred environment template, and instantaneously integrating the preferred environment template into a virtual reality live stream associated with the virtual environment in real-time.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 22, 2024
    Applicant: BANK OF AMERICA CORPORATION
    Inventors: Suryanarayan Parthasarathi Chakravarthi, Pritika Bhatia, Harshit Bhatt, Saisrikanth Chitty, Neha Jain, Mithun Kumar, Madhumitha Swaminathan Rangarajan
  • Patent number: 11895834
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are between immediately-laterally-adjacent of the memory blocks. Conductor material is in and extends elevationally along sidewalls of the trenches laterally-over the conductive tiers and the insulative tiers and directly electrically couples together conducting material of individual of the conductive tiers. The conductor material is exposed to oxidizing conditions to form an insulative oxide laterally-through the conductor material laterally-over individual of the insulative tiers to separate the conducting material of the individual conductive tiers from being directly electrically coupled together by the conductor material. Additional embodiments are disclosed.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jiewei Chen, Jordan D. Greenlee, Mithun Kumar Ramasahayam, Nancy M. Lomeli
  • Publication number: 20230395510
    Abstract: Microelectronic devices include a stack with a vertically alternating sequence of insulative and conductive structures arranged in tiers. A staircased stadium within the stack comprises steps at different tier elevations of a group of the tiers. Treads of the steps are each provided by an upper surface area of one of the conductive structures within the group of the tiers and by an upper surface area of a metal oxide region extending through the one of the conductive structures. A pair of conductive contact structures extends to one of the steps. A first conductive contact structure of the pair terminates at the tread of the step, within the area of the conductive structure. A second conductive contact structure of the pair extends through the tread of the step, within the upper surface area of the metal oxide region. Related fabrication methods and electronic systems are also disclosed.
    Type: Application
    Filed: July 12, 2022
    Publication date: December 7, 2023
    Inventors: Mithun Kumar Ramasahayam, Jordan D. Greenlee, Harsh Narendrakumar Jain, Jiewei Chen, Indra V. Chary
  • Publication number: 20230335193
    Abstract: A microelectronic device comprises a stack structure comprising blocks each including a vertically alternating sequence of conductive material and insulative material arranged in tiers, at least one of the blocks comprising: a memory array region having vertically extending strings of memory cells within a horizontal area thereof; and a staircase region horizontally neighboring the memory array region. The staircase structure has steps comprising horizontal ends of the tiers; and a crest sub-region horizontally interposed between the staircase structure and the memory array region. A masking structure overlies the stack structure and has a different material composition than each of the conductive material and the insulative material. Filled slot structures are interposed between the blocks of the stack structure, at least one of the filled slot structures comprises at least one fill material that has an uppermost boundary vertically underlying an uppermost boundary of the masking structure.
    Type: Application
    Filed: April 13, 2022
    Publication date: October 19, 2023
    Inventors: Shuangqiang Luo, Indra V. Chary, Mithun Kumar Ramasahayam
  • Publication number: 20230259594
    Abstract: Disclosed are systems, apparatuses, processes, and computer-readable media to implement a heterogenous biometric authentication process in a control system. For example, a method may include detecting the presence of a first person at a first time period and in an area associated with a function controlled by a control system. The method may include transmitting an authentication request to a first device detected by the control system, and receiving an authentication response from the first device. The authentication response includes information related to a biometric authentication performed at the first device. The method may further include authenticating the first person in the control system based on the information related to the biometric authentication. The method may then perform the function based on the authentication.
    Type: Application
    Filed: February 11, 2022
    Publication date: August 17, 2023
    Inventors: Dashan GAO, Lei WANG, Ning BI, Mithun Kumar RANGANATH, Chun-Ting HUANG, Scott RUSNAK, David NEAL
  • Publication number: 20230209818
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are between immediately-laterally-adjacent of the memory blocks. Conductor material is in and extends elevationally along sidewalls of the trenches laterally-over the conductive tiers and the insulative tiers and directly electrically couples together conducting material of individual of the conductive tiers. The conductor material is exposed to oxidizing conditions to form an insulative oxide laterally-through the conductor material laterally-over individual of the insulative tiers to separate the conducting material of the individual conductive tiers from being directly electrically coupled together by the conductor material. Additional embodiments are disclosed.
    Type: Application
    Filed: February 17, 2022
    Publication date: June 29, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Jiewei Chen, Jordan D. Greenlee, Mithun Kumar Ramasahayam, Nancy M. Lomeli
  • Publication number: 20230207458
    Abstract: Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods are disclosed. An apparatus includes bit lines including copper, a low-k dielectric material between the bit lines, and air gaps between the bit lines. The low-k dielectric material mechanically supports the bit lines. A method of manufacturing a memory device includes forming a first electrically conductive material in bit line trenches of an electrically insulating material, removing portions of the electrically insulating material between the bit line trenches, conformally forming a low-k dielectric material on the first electrically conductive material and remaining portions of the electrically insulating material, and forming a subconformal dielectric material to form air gaps between the bit line trenches.
    Type: Application
    Filed: October 12, 2022
    Publication date: June 29, 2023
    Inventors: Alyssa N. Scarbrough, David Ross Economy, Jay S. Brown, John D. Hopkins, Jordan D. Greenlee, Mithun Kumar Ramasahayam, Rita J. Klein
  • Publication number: 20230209810
    Abstract: Bit lines having high electrical conductivity and low mutual capacitance and related apparatuses, computing systems, and methods are disclosed. An apparatus includes an electrically insulating material and bit lines including copper in the electrically insulating material. The electrically insulating material defines air gaps between the bit lines. A method of manufacturing a memory device includes forming trenches in an electrically insulating material on or in circuitry of the memory device, forming a first electrically conductive material in the trenches, removing portions of the electrically insulating material to form air gaps between the trenches, recessing the first electrically conductive material, and replacing the first electrically conductive material that was removed with a second electrically conductive material. The second electrically conductive material is more electrically conductive than the first electrically conductive material. A memory device includes the apparatus.
    Type: Application
    Filed: October 12, 2022
    Publication date: June 29, 2023
    Inventors: Alyssa N. Scarbrough, David Ross Economy, John D. Hopkins, Jordan D. Greenlee, Mithun Kumar Ramasahayam
  • Publication number: 20230081678
    Abstract: An electronic device that comprises bitlines and air gaps adjacent to an array region of an electronic device is disclosed. The bitlines comprise sloped sidewalls and a height of the air gaps is greater than a height of the bitlines. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.
    Type: Application
    Filed: November 8, 2022
    Publication date: March 16, 2023
    Inventors: Mithun Kumar Ramasahayam, Michael J. Gossman
  • Patent number: 11508421
    Abstract: An electronic device that comprises bitlines and air gaps adjacent to an array region of an electronic device is disclosed. The bitlines comprise sloped sidewalls and a height of the air gaps is greater than a height of the bitlines. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: November 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Mithun Kumar Ramasahayam, Michael J. Gossman
  • Patent number: 11425031
    Abstract: Examples disclosed herein relate to establishing a layer 3 (L3) Multi-Chassis Link Aggregation Group (MC-LAG). In an example, a common IP address and a common MAC address may be associated with a primary network device and a secondary network device. A layer 3 MC-LAG may be established in a multi-homing configuration between the primary network device and the secondary network device to provide a redundant L3 connectivity to a core network device in a network. A dedicated communication link may be established between the primary network device and the secondary network device, for the primary network device and the secondary network device to share network packets.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: August 23, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Tathagata Nandy, Venkatavaradhan Devarajan, Mithun Kumar Halder
  • Publication number: 20220229841
    Abstract: A specification of data to be obtained from an external database during execution of an automated process configured using the process automation environment is received via a user interface of a process automation environment. An indication of the data to be obtained from the external database is provided to an intermediary server, wherein the intermediary server requests and obtains the data from the external database and sends a stream of the obtained data of the external database. The stream of the obtained data of the external database is received from the intermediary server. The obtained data of the external database is used in the automated process of the process automation environment.
    Type: Application
    Filed: January 20, 2021
    Publication date: July 21, 2022
    Inventors: Chandra Mouli Kharidehal, Joshua Timothy Nerius, Lakshmana Sambasiva Srinivas Kothuri, Mithun Kumar Reddy Gaddam
  • Publication number: 20220157354
    Abstract: An electronic device that comprises bitlines and air gaps adjacent to an array region of an electronic device is disclosed. The bitlines comprise sloped sidewalls and a height of the air gaps is greater than a height of the bitlines. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 19, 2022
    Inventors: Mithun Kumar Ramasahayam, Michael J. Gossman