Patents by Inventor Mithuna S. Thottethodi
Mithuna S. Thottethodi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11068403Abstract: A data processing system includes a memory device; buffer entries each including a plurality of slabs; a prefetch circuit configured to prefetch data from the memory device and store the data in the buffer entries; and processing circuits respectively corresponding to the slabs, each processing circuit being configured to sequentially demand-fetch and process data stored in corresponding slabs in the buffer entries, wherein each processing circuit checks, when demand-fetching data from a first slab among corresponding slabs, a prefetch trigger bit of a first buffer entry in which the first slab is included, determines, when it is determined that the prefetch trigger bit is set, whether all data stored in the slabs included in a second buffer entry is demand-fetched, and triggers, when it is determined that all the data is demand-fetched, the prefetch circuit to perform prefetch of subsequent data to the second buffer entry.Type: GrantFiled: October 2, 2019Date of Patent: July 20, 2021Assignees: SK hynix Inc., Purdue Research FoundationInventors: Il Park, T. N. Vijaykumar, Mithuna S Thottethodi, Nitin Delhi
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Publication number: 20200371941Abstract: A data processing system includes a memory device; buffer entries each including a plurality of slabs; a prefetch circuit configured to prefetch data from the memory device and store the data in the buffer entries; and processing circuits respectively corresponding to the slabs, each processing circuit being configured to sequentially demand-fetch and process data stored in corresponding slabs in the buffer entries, wherein each processing circuit checks, when demand-fetching data from a first slab among corresponding slabs, a prefetch trigger bit of a first buffer entry in which the first slab is included, determines, when it is determined that the prefetch trigger bit is set, whether all data stored in the slabs included in a second buffer entry is demand-fetched, and triggers, when it is determined that all the data is demand-fetched, the prefetch circuit to perform prefetch of subsequent data to the second buffer entry.Type: ApplicationFiled: October 2, 2019Publication date: November 26, 2020Applicants: SK hynix Inc., Purdue Research FoundationInventors: Il PARK, T. N. Vijaykumar, Mithuna S Thottethodi, Nitin Delhi
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Patent number: 9825843Abstract: An electronic assembly includes horizontally-stacked die disposed at an interposer, and may also include vertically-stacked die. The stacked die are interconnected via a multi-hop communication network that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by the intra-die interconnects in a single die and by the inter-die interconnects connecting vertically-stacked sets of die. The router partition is implemented at some or all of the die disposed at the interposer and comprises the logic that supports the functions that route packets among the components of the processing system via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables or configurable logic blocks.Type: GrantFiled: May 18, 2015Date of Patent: November 21, 2017Assignee: Advanced Micro Devices, Inc.Inventors: Mithuna S. Thottethodi, Gabriel H. Loh
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Patent number: 9766936Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism performs a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the resource is not available for performing the operation and until another resource is selected for performing the operation, the selection mechanism identifies a next resource in the table and selects the next resource for performing the operation when the next resource is available for performing the operation.Type: GrantFiled: November 6, 2015Date of Patent: September 19, 2017Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Bradford M. Beckmann, Mithuna S. Thottethodi, James M. O'Connor, Mauricio Breternitz, Lisa R. Hsu, Gabriel H. Loh, Yasuko Eckert
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Patent number: 9710392Abstract: Embodiments are described for methods and systems for mapping virtual memory pages to physical memory pages by analyzing a sequence of memory-bound accesses to the virtual memory pages, determining a degree of contiguity between the accessed virtual memory pages, and mapping sets of the accessed virtual memory pages to respective single physical memory pages. Embodiments are also described for a method for increasing locality of memory accesses to DRAM in virtual memory systems by analyzing a pattern of virtual memory accesses to identify contiguity of accessed virtual memory pages, predicting contiguity of the accessed virtual memory pages based on the pattern, and mapping the identified and predicted contiguous virtual memory pages to respective single physical memory pages.Type: GrantFiled: August 15, 2014Date of Patent: July 18, 2017Assignee: Advanced Micro Devices, Inc.Inventors: Syed Ali Jafri, Yasuko Eckert, Srilatha Manne, Mithuna S Thottethodi
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Patent number: 9552294Abstract: The described embodiments include a main memory and a cache memory (or “cache”) with a cache controller that includes a mode-setting mechanism. In some embodiments, the mode-setting mechanism is configured to dynamically determine an access pattern for the main memory. Based on the determined access pattern, the mode-setting mechanism configures at least one region of the main memory in a write-back mode and configures other regions of the main memory in a write-through mode. In these embodiments, when performing a write operation in the cache memory, the cache controller determines whether a region in the main memory where the cache block is from is configured in the write-back mode or the write-through mode and then performs a corresponding write operation in the cache memory.Type: GrantFiled: January 7, 2013Date of Patent: January 24, 2017Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Jaewoong Sim, Mithuna S. Thottethodi, Gabriel H. Loh
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Patent number: 9529718Abstract: To efficiently transfer of data from a cache to a memory, it is desirable that more data corresponding to the same page in the memory be loaded in a line buffer. Writing data to a memory page that is not currently loaded in a row buffer requires closing an old page and opening a new page. Both operations consume energy and clock cycles and potentially delay more critical memory read requests. Hence it is desirable to have more than one write going to the same DRAM page to amortize the cost of opening and closing DRAM pages. A desirable approach is batch write backs to the same DRAM page by retaining modified blocks in the cache until a sufficient number of modified blocks belonging to the same memory page are ready for write backs.Type: GrantFiled: December 12, 2014Date of Patent: December 27, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Syed Ali R. Jafri, Yasuko Eckert, Srilatha Manne, Mithuna S. Thottethodi, Gabriel H. Loh
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Publication number: 20160170887Abstract: To efficiently transfer of data from a cache to a memory, it is desirable that more data corresponding to the same page in the memory be loaded in a line buffer. Writing data to a memory page that is not currently loaded in a row buffer requires closing an old page and opening a new page. Both operations consume energy and clock cycles and potentially delay more critical memory read requests. Hence it is desirable to have more than one write going to the same DRAM page to amortize the cost of opening and closing DRAM pages. A desirable approach is batch write backs to the same DRAM page by retaining modified blocks in the cache until a sufficient number of modified blocks belonging to the same memory page are ready for write backs.Type: ApplicationFiled: December 12, 2014Publication date: June 16, 2016Inventors: Syed Ali R. JAFRI, Yasuko ECKERT, Srilatha MANNE, Mithuna S. THOTTETHODI, Gabriel H. LOH
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Publication number: 20160062803Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism performs a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the resource is not available for performing the operation and until another resource is selected for performing the operation, the selection mechanism identifies a next resource in the table and selects the next resource for performing the operation when the next resource is available for performing the operation.Type: ApplicationFiled: November 6, 2015Publication date: March 3, 2016Inventors: Bradford M. Beckmann, Mithuna S. Thottethodi, James M. O'Connor, Mauricio Breternitz, Lisa R. Hsu, Gabriel H. Loh, Yasuko Eckert
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Publication number: 20160049181Abstract: Embodiments are described for methods and systems for mapping virtual memory pages to physical memory pages by analyzing a sequence of memory-bound accesses to the virtual memory pages, determining a degree of contiguity between the accessed virtual memory pages, and mapping sets of the accessed virtual memory pages to respective single physical memory pages. Embodiments are also described for a method for increasing locality of memory accesses to DRAM in virtual memory systems by analyzing a pattern of virtual memory accesses to identify contiguity of accessed virtual memory pages, predicting contiguity of the accessed virtual memory pages based on the pattern, and mapping the identified and predicted contiguous virtual memory pages to respective single physical memory pages.Type: ApplicationFiled: August 15, 2014Publication date: February 18, 2016Inventors: Syed Ali Jafri, Yasuko Eckert, Srilatha Manne, Mithuna S. Thottethodi
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Patent number: 9251069Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, wherein a first bank is powered down. In response a write request to a second bank for data indicated to be stored in the powered down first bank, the cache controller determines a respective bypass condition for the data. If the bypass condition exceeds a threshold, then the cache controller invalidates any copy of the data stored in the second bank. If the bypass condition does not exceed the threshold, then the cache controller stores the data with a clean state in the second bank. The cache controller writes the data in a lower-level memory for both cases.Type: GrantFiled: October 16, 2013Date of Patent: February 2, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Yasuko Eckert, Gabriel H. Loh, Mauricio Breternitz, James M. O'Connor, Srilatha Manne, Nuwan S. Jayasena, Mithuna S. Thottethodi
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Publication number: 20150357306Abstract: An electronic assembly includes horizontally-stacked die disposed at an interposer, and may also include vertically-stacked die. The stacked die are interconnected via a multi-hop communication network that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by the intra-die interconnects in a single die and by the inter-die interconnects connecting vertically-stacked sets of die. The router partition is implemented at some or all of the die disposed at the interposer and comprises the logic that supports the functions that route packets among the components of the processing system via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables or configurable logic blocks.Type: ApplicationFiled: May 18, 2015Publication date: December 10, 2015Inventors: Mithuna S. Thottethodi, Gabriel H. Loh
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Patent number: 9183055Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism is configured to perform a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the identified resource is not available for performing the operation and until a resource is selected for performing the operation, the selection mechanism is configured to identify a next resource in the table and select the next resource for performing the operation when the next resource is available for performing the operation.Type: GrantFiled: February 7, 2013Date of Patent: November 10, 2015Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Bradford M. Beckmann, Mithuna S. Thottethodi, James M. O'Connor, Mauricio Breternitz, Lisa R. Hsu, Gabriel H. Loh, Yasuko Eckert
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Patent number: 9075730Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache and one or more sources for memory requests. In response to receiving a request to allocate data of a first type, a cache controller allocates the data in the cache responsive to determining a limit of an amount of data of the first type permitted in the cache is not reached. The controller maintains an amount and location information of the data of the first type stored in the cache. Additionally, the cache may be partitioned with each partition designated for storing data of a given type. Allocation of data of the first type is dependent at least upon the availability of a first partition and a limit of an amount of data of the first type in a second partition.Type: GrantFiled: December 21, 2012Date of Patent: July 7, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Mithuna S. Thottethodi, Gabriel H. Loh, James M. O'Connor, Yasuko Eckert, Bradford M. Beckmann
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Patent number: 9065722Abstract: An electronic assembly includes horizontally-stacked die disposed at an interposer, and may also include vertically-stacked die. The stacked die are interconnected via a multi-hop communication network that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by the intra-die interconnects in a single die and by the inter-die interconnects connecting vertically-stacked sets of die. The router partition is implemented at some or all of the die disposed at the interposer and comprises the logic that supports the functions that route packets among the components of the processing system via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables or configurable logic blocks.Type: GrantFiled: December 23, 2012Date of Patent: June 23, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Mithuna S. Thottethodi, Gabriel H. Loh
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Publication number: 20140223445Abstract: The described embodiments comprise a selection mechanism that selects a resource from a set of resources in a computing device for performing an operation. In some embodiments, the selection mechanism is configured to perform a lookup in a table selected from a set of tables to identify a resource from the set of resources. When the identified resource is not available for performing the operation and until a resource is selected for performing the operation, the selection mechanism is configured to identify a next resource in the table and select the next resource for performing the operation when the next resource is available for performing the operation.Type: ApplicationFiled: February 7, 2013Publication date: August 7, 2014Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Bradford M. Beckmann, Mithuna S. Thottethodi, James M. O'Connor, Mauricio Breternitz, Lisa R. Hsu, Gabriel H. Loh, Yasuko Eckert
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Publication number: 20140181414Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache array and a corresponding cache controller. The cache array includes multiple banks, wherein a first bank is powered down. In response a write request to a second bank for data indicated to be stored in the powered down first bank, the cache controller determines a respective bypass condition for the data. If the bypass condition exceeds a threshold, then the cache controller invalidates any copy of the data stored in the second bank. If the bypass condition does not exceed the threshold, then the cache controller stores the data with a clean state in the second bank. The cache controller writes the data in a lower-level memory for both cases.Type: ApplicationFiled: October 16, 2013Publication date: June 26, 2014Applicant: Advanced Micro Devices, Inc.Inventors: Yasuko Eckert, Gabriel H. Loh, Mauricio Breternitz, James M. O'Connor, Srilatha Manne, Nuwan S. Jayasena, Mithuna S. Thottethodi
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Publication number: 20140177626Abstract: An electronic assembly includes horizontally-stacked die disposed at an interposer, and may also include vertically-stacked die. The stacked die are interconnected via a multi-hop communication network that is partitioned into a link partition and a router partition. The link partition is at least partially implemented in the metal layers of the interposer for horizontally-stacked die. The link partition may also be implemented in part by the intra-die interconnects in a single die and by the inter-die interconnects connecting vertically-stacked sets of die. The router partition is implemented at some or all of the die disposed at the interposer and comprises the logic that supports the functions that route packets among the components of the processing system via the interconnects of the link partition. The router partition may implement fixed routing, or alternatively may be configurable using programmable routing tables or configurable logic blocks.Type: ApplicationFiled: December 23, 2012Publication date: June 26, 2014Applicant: Advanced Micro Devices, Inc.Inventors: Mithuna S. Thottethodi, Gabriel H. Loh
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Publication number: 20140181412Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache and one or more sources for memory requests. In response to receiving a request to allocate data of a first type, a cache controller allocates the data in the cache responsive to determining a limit of an amount of data of the first type permitted in the cache is not reached. The controller maintains an amount and location information of the data of the first type stored in the cache. Additionally, the cache may be partitioned with each partition designated for storing data of a given type. Allocation of data of the first type is dependent at least upon the availability of a first partition and a limit of an amount of data of the first type in a second partition.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Mithuna S. Thottethodi, Gabriel H. Loh, James M. O'Connor, Yasuko Eckert, Bradford M. Beckmann
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Publication number: 20140143505Abstract: The described embodiments include a main memory and a cache memory (or “cache”) with a cache controller that includes a mode-setting mechanism. In some embodiments, the mode-setting mechanism is configured to dynamically determine an access pattern for the main memory. Based on the determined access pattern, the mode-setting mechanism configures at least one region of the main memory in a write-back mode and configures other regions of the main memory in a write-through mode.Type: ApplicationFiled: January 7, 2013Publication date: May 22, 2014Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Jaewoong Sim, Mithuna S. Thottethodi, Gabriel H. Loh