Patents by Inventor Miti Joshi

Miti Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Testbench for sub-design verification
    Patent number: 12271670
    Abstract: Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list is logged in a switching activity file while running a circuit design testbench for the circuit design with the selected sub-design in scope. From the list, the switching activity, and the one or more parameter values, a sub-design testbench for the selected sub-design is generated.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: April 8, 2025
    Assignee: Xilinx, Inc.
    Inventors: Rajvinder S. Klair, Dhiraj Kumar Prasad, Saikat Bandyopadhyay, Ashish Kumar Jain, Shiyao Ge, Tapodyuti Mandal, Miti Joshi
  • TESTBENCH FOR SUB-DESIGN VERIFICATION
    Publication number: 20230252212
    Abstract: Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list is logged in a switching activity file while running a circuit design testbench for the circuit design with the selected sub-design in scope. From the list, the switching activity, and the one or more parameter values, a sub-design testbench for the selected sub-design is generated.
    Type: Application
    Filed: February 4, 2022
    Publication date: August 10, 2023
    Applicant: Xilinx, Inc.
    Inventors: Rajvinder S. Klair, Dhiraj Kumar Prasad, Saikat Bandyopadhyay, Ashish Kumar Jain, Shiyao Ge, Tapodyuti Mandal, Miti Joshi