Abstract: A field programmable gate array (FPGA) may be used for inference of a trained deep neural network (DNN). The trained DNN may comprise a set of parameters and the FPGA may have a first precision configuration defining first number representations of the set of parameters. The FPGA may determine different precision configurations of the trained DNN. A precision configuration of the precision configurations may define second number representations of a subset of the set of parameters. For each precision configuration of the determined precision configurations a bitstream file may be provided. The bitstream files may be stored so that the FPGA may be programmed using one of the stored bitstream files for inference of the trained DNN.

Abstract: The present disclosure relates to a messaging method for a hardware acceleration system. The method includes determining exchange message types to be exchanged with a hardware accelerator in accordance with an application performed by the hardware acceleration system. The exchange message types indicate a number of variables, and a type of the variables, of the messages. The method also includes selecting schemas from a schema database. The message type schemas indicates a precision representation of variables of messages associated with the schema. The selected schemas correspond to the determined exchange message types. Further, the method includes configuring a serial interface of the hardware accelerator in accordance with the selected schemas, to enable a message exchange including the messages.

Abstract: A random sequence generation of defined values may be provided. A method comprises pre-loading a RAM block with an initial list comprising the defined values of a sequence of values to be updated, and shuffling the defined values of the sequence using a counter and a random offset for indices in the list.

Abstract: Analysis of genetic disease progression may be provided. Data about a set of molecular status may be received. A dynamic prediction model of molecular interactions may be provided over time. The molecular statuses of the set over time may be determined using the dynamic prediction model. The determined molecular statuses may be clustered by applying an interaction-aware metric for the analysis of the genetic disease progression.

Abstract: Computer-implemented methods are provided for generating a personalized Boolean model for a genetic disease of a patient. The method includes storing specification data and reference model data. The reference model includes gene nodes, representing genes, connected to Boolean circuitry and a plurality of inputs for receiving binary input values. Each gene node in the reference model comprises a multiplexer. The multiplexer has a first input and an output, a second input for receiving a binary mutation value, and a control input for receiving a binary selector value. The method further comprises using a model checker to determine if the specification is reachable in the reference model. If the specification is reachable, the method includes identifying each multiplexer whose second input was connected to its output in the path reaching the specification to obtain mutation data for the patient, generating a personalized Boolean model, and outputting personal model data.

Abstract: An example of an embodiment is directed to a computer-implemented method for providing a cloud service to execute a computing task of a model specification. The method includes receiving, by the cloud service, the model specification and input data for the model specification from a user. The method further includes generating, by the cloud service, native code from the model specification and executing, by the cloud service, the computing task by executing the native code as a native process with the input data. The method also includes providing, by the cloud service, results of the computing task to the user. Other embodiments further concern a related computing system and a related computer program product.

Abstract: The present disclosure relates to a messaging method for a hardware acceleration system. The method includes determining exchange message types to be exchanged with a hardware accelerator in accordance with an application performed by the hardware acceleration system. The exchange message types indicate a number of variables, and a type of the variables, of the messages. The method also includes selecting schemas from a schema database. The message type schemas indicates a precision representation of variables of messages associated with the schema. The selected schemas correspond to the determined exchange message types. Further, the method includes configuring a serial interface of the hardware accelerator in accordance with the selected schemas, to enable a message exchange including the messages.

Abstract: Generating an abstract model of the behavior of a hardware and/or software design. A learning framework learns an unknown regular language that represents the behaviors of the hardware and/or software logic which do not violate a specified property that the abstract model is required to satisfy. The framework receives input data including the specified property, concrete models of the behavior of the hardware and/or software; and an alphabet of all symbols that are allowed to occur in any string that can be defined in the unknown regular language, each symbol representing an event in the hardware and/or software. The framework generates an abstract model of the behavior of the hardware or software design by checking whether a sequence of events in a concrete model satisfies the specified property and outputs the generated abstract model.

Abstract: A field programmable gate array (FPGA) may be used for inference of a trained deep neural network (DNN). The trained DNN may comprise a set of parameters and the FPGA may have a first precision configuration defining first number representations of the set of parameters. The FPGA may determine different precision configurations of the trained DNN. A precision configuration of the precision configurations may define second number representations of a subset of the set of parameters. For each precision configuration of the determined precision configurations a bitstream file may be provided. The bitstream files may be stored so that the FPGA may be programmed using one of the stored bitstream files for inference of the trained DNN.

Abstract: Analysis of genetic disease progression may be provided. Data about a set of molecular status may be received. A dynamic prediction model of molecular interactions may be provided over time. The molecular statuses of the set over time may be determined using the dynamic prediction model. The determined molecular statuses may be clustered by applying an interaction-aware metric for the analysis of the genetic disease progression.

Abstract: An example of an embodiment is directed to a computer-implemented method for providing a cloud service to execute a computing task of a model specification. The method includes receiving, by the cloud service, the model specification and input data for the model specification from a user. The method further includes generating, by the cloud service, native code from the model specification and executing, by the cloud service, the computing task by executing the native code as a native process with the input data. The method also includes providing, by the cloud service, results of the computing task to the user. Other embodiments further concern a related computing system and a related computer program product.

Abstract: A random sequence generation of defined values may be provided. A method comprises pre-loading a RAM block with an initial list comprising the defined values of a sequence of values to be updated, and shuffling the defined values of the sequence using a counter and a random offset for indices in the list.

Abstract: Generating an abstract model of the behavior of a hardware and/or software design. A learning framework learns an unknown regular language that represents the behaviors of the hardware and/or software logic which do not violate a specified property that the abstract model is required to satisfy. The framework receives input data including the specified property, concrete models of the behavior of the hardware and/or software; and an alphabet of all symbols that are allowed to occur in any string that can be defined in the unknown regular language, each symbol representing an event in the hardware and/or software. The framework generates an abstract model of the behavior of the hardware or software design by checking whether a sequence of events in a concrete model satisfies the specified property and outputs the generated abstract model.

Abstract: Computer-implemented methods are provided for generating a personalized Boolean model for a genetic disease of a patient. The method includes storing specification data and reference model data. The reference model includes gene nodes, representing genes, connected to Boolean circuitry and a plurality of inputs for receiving binary input values. Each gene node in the reference model comprises a multiplexer. The multiplexer has a first input and an output, a second input for receiving a binary mutation value, and a control input for receiving a binary selector value. The method further comprises using a model checker to determine if the specification is reachable in the reference model. If the specification is reachable, the method includes identifying each multiplexer whose second input was connected to its output in the path reaching the specification to obtain mutation data for the patient, generating a personalized Boolean model, and outputting personal model data.

Abstract: A method for formally verifying a hardware/software co-design includes providing in a co-design, a first model, and a second model, the first model is one of a hardware model, and the second model is one of a software model, or vice versa, providing a safety property expected to be satisfied by the co-design, combining an abstraction of the first model and the safety property to obtain an abstracted first model, composing the abstracted first model and the second model to obtain a composed model, checking if the composed model satisfies the safety property, and signaling that the hardware/software co-design violates the safety property if the safety property is violated in the composed model.

Abstract: A method for formally verifying a hardware/software co-design includes providing in a co-design, a first model, and a second model, the first model is one of a hardware model, and the second model is one of a software model, or vice versa, providing a safety property expected to be satisfied by the co-design, combining an abstraction of the first model and the safety property to obtain an abstracted first model, composing the abstracted first model and the second model to obtain a composed model, checking if the composed model satisfies the safety property, and signaling that the hardware/software co-design violates the safety property if the safety property is violated in the composed model.

Abstract: A method for formally verifying a hardware/software co-design includes providing in a co-design, a first model, and a second model, the first model is one of a hardware model, and the second model is one of a software model, or vice versa, providing a safety property expected to be satisfied by the co-design, combining an abstraction of the first model and the safety property to obtain an abstracted first model, composing the abstracted first model and the second model to obtain a composed model, checking if the composed model satisfies the safety property, and signaling that the hardware/software co-design violates the safety property if the safety property is violated in the composed model.

Abstract: A method for formally verifying a hardware/software co-design includes providing in a co-design, a first model, and a second model, the first model is one of a hardware model, and the second model is one of a software model, or vice versa, providing a safety property expected to be satisfied by the co-design, combining an abstraction of the first model and the safety property to obtain an abstracted first model, composing the abstracted first model and the second model to obtain a composed model, checking if the composed model satisfies the safety property, and signaling that the hardware/software co-design violates the safety property if the safety property is violated in the composed model.

Abstract: Embodiments include dividing source code for an application into multiple program fragments by generating a control flow graph for the multiple program fragments. The control flow graph represents a graph structure with nodes representing the multiple program fragments and edges representing an execution order of the program fragments. Aspects include searching for a chosen assertion statement within a program fragment, wherein the chosen assertion statement must be satisfied for correct execution of the chosen program fragment. Aspects also include identifying an immediate parent program fragment for the chosen program fragment using the control flow graph and calculating an immediate parent assertion statement for the immediate parent program fragment using the chosen assertion logic statement. The immediate parent assertion statement is an over-approximate pre-condition of the chosen program fragment.

Abstract: A method for determining correctness of a transformation between a first finite state automaton (FSA) and a second FSA, wherein the first FSA comprises a representation of a regular expression, and the second FSA comprises a transformation of the first FSA includes determining a third FSA, the third FSA comprising a cross product of the second FSA and a post-processor; determining whether the first FSA and the third FSA are equivalent; and in the event that the first FSA is determined not to be equivalent to the third FSA, determining that the transformation between the first FSA and the second FSA is not correct.