Patents by Inventor Mitsuaki Furumoto

Mitsuaki Furumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of designing a semiconductor circuit and a semiconductor circuit designed using the method
    Publication number: 20010054171
    Abstract: In the method of designing a semiconductor circuit having clock trees, a netlist is first generated. Then, a delay gates are inserted onto said netlist. Finally, inserted extra delay gates are deleted based on a timing constraint the clock trees is satisfied or not. As a consequence, skew between the clock trees can be easily adjusted.
    Type: Application
    Filed: December 5, 2000
    Publication date: December 20, 2001
    Inventors: Mitsuaki Furumoto, Hiroomi Nakao