Patents by Inventor Mitsuaki Harada

Mitsuaki Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7999786
    Abstract: To reduce or prevent metal wirings formed on one substrate and electrodes formed on the other substrate from being shorted. An electrophoretic display in which, a display part including electrophoretic particles electrophoresed by application of an electric field, and an electrophoretic display part including an electrode to apply the electric field to the display part, are bonded to a substrate. The substrate includes a metal wiring including an insulating part disposed at a position that corresponds to at least a part of an edge of the electrode.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: August 16, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Mitsuaki Harada, Takeo Kawase, Soichi Moriya
  • Patent number: 7589018
    Abstract: A method of forming a contact hole includes forming a first conductive layer patterned so as to serve as an electrode or a wiring on a substrate, forming an insulation layer on the substrate and the first conductive layer, inserting a cutting instrument into the insulation layer at an angle to a surface of the insulation layer, the angle being in the range from 5° to 80°, and forming a tapered opening extending to the electrode or the wiring in the insulation layer by drawing out the cutting instrument.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: September 15, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Soichi Moriya, Takeo Kawase, Mitsuaki Harada, Takehisa Saeki, Tomoyuki Okuyama, Hirofumi Hokari, Takashi Aoki
  • Patent number: 7459793
    Abstract: A method for forming a contact hole, a method for manufacturing a circuit board and a method for manufacturing an electro-optical device that increase the reliability of electrical coupling via a conductive part and prevent wire-breaking due to projections when forming a contact hole in an interlayer film by using a needle, and burying a conductive material in the contact hole is provided.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: December 2, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Mitsuaki Harada, Soichi Moriya
  • Patent number: 7425474
    Abstract: A method of manufacturing a transistor includes the step of forming on a substrate a source electrode and drain electrode by selective electroless plating after patterning a charge control agent attached to the substrate using light, and the step of forming an organic semiconductor, a gate insulation layer, and a gate electrode.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: September 16, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Takeo Kawase, Satoshi Kimura, Hidemichi Furihata, Mitsuaki Harada
  • Patent number: 7399989
    Abstract: An electrode is provided that is economically produced and capable of efficiently injecting holes. Also provided are a method to form an electrode that is capable of easily manufacturing such an electrode, a highly reliable thin-film transistor, an electronic circuit using this thin-film transistor, an organic electroluminescent element, a display, and electronic equipment. A thin-film transistor is a top-gate thin-film transistor. The thin-film transistor includes a source electrode and a drain electrode that are placed separately from each other. The thin-film transistor also includes an organic semiconductor layer that is laid out between the source electrode and the drain electrode, and a gate insulating layer that is provided between the organic semiconductor layer and a gate electrode. This structure is mounted on a substrate. Each of the source electrode and the drain electrode is composed of two layers, that is, an underlying electrode layer and a surface electrode layer.
    Type: Grant
    Filed: August 2, 2004
    Date of Patent: July 15, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Soichi Moriya, Takeo Kawase, Mitsuaki Harada
  • Publication number: 20080113466
    Abstract: A method of forming a contact hole includes forming a first conductive layer patterned so as to serve as an electrode or a wiring on a substrate, forming an insulation layer on the substrate and the first conductive layer, inserting a cutting instrument into the insulation layer at an angle to a surface of the insulation layer, the angle being in the range from #5#° to~ 80#°, and forming a tapered opening extending to the electrode or the wiring in the insulation layer by drawing out the cutting instrument.
    Type: Application
    Filed: October 5, 2007
    Publication date: May 15, 2008
    Applicant: Seiko Epson Corporation
    Inventors: Soichi Moriya, Takeo Kawase, Mitsuaki Harada, Takehisa Saeki, Tomoyuki Okuyama, Hirofumi Hokari, Takashi Aoki
  • Patent number: 7361927
    Abstract: A transistor having at least one of a source electrode and a drain electrode being formed of a porous film is described. The transistor maintains its characteristics even after being subjected to a high temperature and high humidity environment. The transistor may be used in a circuit board, a display and electronic equipment.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: April 22, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Takeo Kawase, Soichi Moriya, Mitsuaki Harada
  • Patent number: 7361594
    Abstract: Aspects of the invention can provide a method of manufacturing a thin film transistor capable of manufacturing a high-performance thin film transistor with a simple process, a thin film transistor manufactured using the method of manufacturing a thin film transistor, and a thin film transistor circuit, an electronic device, and an electronic apparatus each equipped with the thin film transistor.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: April 22, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Takeo Kawase, Mitsuaki Harada, Satoshi Kimura, Hidemichi Furihata
  • Patent number: 7358118
    Abstract: Aspects of the current invention are directed to a method of mounting a flexible printed circuit and a manufacturing method of an electric optical device. Each of the methods form semiconductor elements and first terminal portions for electrically connecting the semiconductor elements and the outside of the board. These terminal portions have are completely or partially covered with an organic film 37 and are pressed into second terminal portion on the flexible printed circuit from the direction above the organic film thereby creating an electrical connection. Optionally, an anisotropic conductive paste or anisotropic conductive film may be provided between the second terminal portion and the organic film.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: April 15, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Mitsuaki Harada, Soichi Moriya, Takeo Kawase, Atsushi Miyazaki
  • Patent number: 7199049
    Abstract: A method for forming a contact hole, a method for manufacturing a circuit board and a method for manufacturing an electro-optical device that increase the reliability of electrical coupling via a conductive part and prevent wire-breaking due to projections when forming a contact hole in an interlayer film by using a needle, and burying a conductive material in the contact hole is provided.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: April 3, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Mitsuaki Harada, Soichi Moriya
  • Patent number: 7180108
    Abstract: A transistor having at least one of a source electrode and a drain electrode being formed of a porous film is described. The transistor maintains its characteristics even after being subjected to a high temperature and high humidity environment. The transistor may be used in a circuit board, a display and electronic equipment.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: February 20, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Takeo Kawase, Soichi Moriya, Mitsuaki Harada
  • Publication number: 20060267005
    Abstract: A transistor having at least one of a source electrode and a drain electrode being formed of a porous film is described. The transistor maintains its characteristics even after being subjected to a high temperature and high humidity environment. The transistor may be used in a circuit board, a display and electronic equipment.
    Type: Application
    Filed: August 7, 2006
    Publication date: November 30, 2006
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Takeo Kawase, Soichi Moriya, Mitsuaki Harada
  • Publication number: 20060263945
    Abstract: A method for forming a contact hole, a method for manufacturing a circuit board and a method for manufacturing an electro-optical device that increase the reliability of electrical coupling via a conductive part and prevent wire-breaking due to projections when forming a contact hole in an interlayer film by using a needle, and burying a conductive material in the contact hole is provided.
    Type: Application
    Filed: July 31, 2006
    Publication date: November 23, 2006
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Mitsuaki HARADA, Soichi MORIYA
  • Publication number: 20060023154
    Abstract: Aspects of the current invention are directed to a method of mounting a flexible printed circuit and a manufacturing method of an electric optical device. Each of the methods form semiconductor elements and first terminal portions for electrically connecting the semiconductor elements and the outside of the board. These terminal portions have are completely or partially covered with an organic film 37 and are pressed into second terminal portion on the flexible printed circuit from the direction above the organic film thereby creating an electrical connection. Optionally, an anisotropic conductive paste or anisotropic conductive film may be provided between the second terminal portion and the organic film.
    Type: Application
    Filed: July 26, 2005
    Publication date: February 2, 2006
    Applicant: Seiko Epson Corporation
    Inventors: Mitsuaki Harada, Soichi Moriya, Takeo Kawase, Atsushi Miyazaki
  • Publication number: 20060024957
    Abstract: A method for forming a contact hole, a method for manufacturing a circuit board and a method for manufacturing an electro-optical device that increase the reliability of electrical coupling via a conductive part and prevent wire-breaking due to projections when forming a contact hole in an interlayer film by using a needle, and burying a conductive material in the contact hole is provided.
    Type: Application
    Filed: June 13, 2005
    Publication date: February 2, 2006
    Applicant: Seiko Epson Corporation
    Inventors: Mitsuaki Harada, Soichi Moriya
  • Publication number: 20050186699
    Abstract: A method of manufacturing a transistor includes the step of forming on a substrate a source electrode and drain electrode by selective electroless plating after patterning a charge control agent attached to the substrate using light, and the step of forming an organic semiconductor, a gate insulation layer, and a gate electrode.
    Type: Application
    Filed: February 18, 2005
    Publication date: August 25, 2005
    Applicant: Seiko Epson Corporation
    Inventors: Takeo Kawase, Satoshi Kimura, Hidemichi Furihata, Mitsuaki Harada
  • Publication number: 20050181533
    Abstract: A method for manufacturing an electro-optical device board including on a substrate a switching element and a coupling wiring coupled to the switching element is provided. The method includes the steps of forming the switching element and first coupling wirings simultaneously by patterning using light irradiation; and forming second coupling wirings by an additive patterning process.
    Type: Application
    Filed: January 31, 2005
    Publication date: August 18, 2005
    Applicant: Seiko Epson Corporation
    Inventors: Takeo Kawase, Soichi Moriya, Mitsuaki Harada
  • Publication number: 20050173701
    Abstract: A transistor having at least one of a source electrode and a drain electrode being formed of a porous film is described. The transistor maintains its characteristics even after being subjected to a high temperature and high humidity environment. The transistor may be used in a circuit board, a display and electronic equipment.
    Type: Application
    Filed: February 4, 2005
    Publication date: August 11, 2005
    Applicant: Seiko Epson Corporation
    Inventors: Takeo Kawase, Soichi Moriya, Mitsuaki Harada
  • Publication number: 20050162379
    Abstract: To reduce or prevent metal wirings formed on one substrate and electrodes formed on the other substrate from being shorted. An electrophoretic display in which, a display part including electrophoretic particles electrophoresed by application of an electric field, and an electrophoretic display part including an electrode to apply the electric field to the display part, are bonded to a substrate. The substrate includes a metal wiring including an insulating part disposed at a position that corresponds to at least a part of an edge of the electrode.
    Type: Application
    Filed: January 7, 2005
    Publication date: July 28, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Mitsuaki Harada, Takeo Kawase, Soichi Moriya
  • Publication number: 20050151195
    Abstract: Aspects of the invention can provide a method of manufacturing a thin film transistor capable of manufacturing a high-performance thin film transistor with a simple process, a thin film transistor manufactured using the method of manufacturing a thin film transistor, and a thin film transistor circuit, an electronic device, and an electronic apparatus each equipped with the thin film transistor.
    Type: Application
    Filed: November 16, 2004
    Publication date: July 14, 2005
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Takeo Kawase, Mitsuaki Harada, Satoshi Kimura, Hidemichi Furihata