Abstract: An information processing system includes a control central processing unit a memory; and a stream interface configured to receive an input stream including data to be processed and to transfer the input stream to the memory. A download process in which the stream interface receives stream data including firmware and stores the stream data in the memory is executed in response to an instruction from the control central processing unit, and the control central processing unit analyzes the stream data stored in the memory to extract the firmware in the memory space and executes the firmware extracted in the memory space to process the data to be processed.

Abstract: Instruction cache memory having a plurality of memory (for example, cache WAY), means 3 for storing prediction data of a conditional branch of a branch instruction being taken or not taken and for storing prediction data of memory storing the branch instruction data of the plurality of memory when the prediction is the branch being taken, and means for, when an instruction to be executed is a branch instruction, outputting a read active control signal to the plurality of memories 1 by using two pieces of prediction data obtained from the means by an index corresponding to the branch instruction, are comprised.

Abstract: The present invention is contrived to divide an address for accessing cache memory into a first through a fourth fields from the uppermost bit side, use the first and third fields for respectively storing tag addresses, divide the second and fourth fields into one or more subfields, respectively, use one or more subfields for storing index addresses, and use the remaining subfields for respectively storing line addresses. The second field is handled as one subfield, for example, for storing an index address, and the fourth field is divided into two subfields for storing an index address in one and a line address in the other. Such a configuration manages a form of a block of which data is stored in one entry.

Abstract: A memory cache device in which a storage area used for a memory data protection function is effectively used at the time of not using the memory data protection function. A mode selection signal makes ECC code sections for storing an ECC code function as a storage area for storing ECC codes used for performing error detection or error correction on data stored in data RAMs at the time the memory data protection function is enabled and as a way added to the data RAMs at the time the memory data protection function is disabled.

Abstract: An information processing system includes a control central processing unit a memory; and a stream interface configured to receive an input stream including data to be processed and to transfer the input stream to the memory. A download process in which the stream interface receives stream data including firmware and stores the stream data in the memory is executed in response to an instruction from the control central processing unit, and the control central processing unit analyzes the stream data stored in the memory to extract the firmware in the memory space and executes the firmware extracted in the memory space to process the data to be processed.

Abstract: A transcoder capable of efficiently utilizing a large-capacity storage medium, of efficiently coping with diverse and complex standards, and of reducing power consumption has been described. To the transcoder, first format image data encoded in a first format is input and the transcoder outputs the first format image data and second format image data encoded in a second format different from the first format, wherein the transcoder comprises an interface with a storage device and a storage device control part that controls the storing and reading in the storage device via the interface and simultaneously stores the image data of the first and second formats of the same image in the storage device via the interface.

Abstract: Instruction cache memory having a plurality of memory (for example, cache WAY), means 3 for storing prediction data of a conditional branch of a branch instruction being taken or not taken and for storing prediction data of memory storing the branch instruction data of the plurality of memory when the prediction is the branch being taken, and means for, when an instruction to be executed is a branch instruction, outputting a read active control signal to the plurality of memories 1 by using two pieces of prediction data obtained from the means by an index corresponding to the branch instruction, are comprised.

Abstract: The present invention is contrived to divide an address for accessing cache memory into a first through a fourth fields from the uppermost bit side, use the first and third fields for respectively storing tag addresses, divide the second and fourth fields into one or more subfields, respectively, use one or more subfields for storing index addresses, and use the remaining subfields for respectively storing line addresses. The second field is handled as one subfield, for example, for storing an index address, and the fourth field is divided into two subfields for storing an index address in one and a line address in the other. Such a configuration manages a form of a block of which data is stored in one entry.

Abstract: A memory cache device in which a storage area used for a memory data protection function is effectively used at the time of not using the memory data protection function. A mode selection signal makes ECC code sections for storing an ECC code function as a storage area for storing ECC codes used for performing error detection or error correction on data stored in data RAMs at the time the memory data protection function is enabled and as a way added to the data RAMs at the time the memory data protection function is disabled.

Abstract: The present invention relates to a residual voltage regulating circuit for a Hall element improving the dependency on temperature of the output voltage of the Hall element and the secular changes of the Hall element.