Patents by Inventor Mitsuaki Hori
Mitsuaki Hori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10192866Abstract: A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.Type: GrantFiled: May 25, 2017Date of Patent: January 29, 2019Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kazushi Fujita, Taiji Ema, Mitsuaki Hori, Yasunobu Torii
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Patent number: 10090201Abstract: A semiconductor device manufacturing method includes forming a silicon layer by epitaxial growth over a semiconductor substrate having a first area and a second area; forming a first gate oxide film by oxidizing the silicon layer; removing the first gate oxide film from the second area, while maintaining the first gate oxide film in the first area; thereafter, increasing a thickness of the first gate oxide film in the first area and simultaneously forming a second gate oxide film by oxidizing the silicon layer in the second area; and forming a first gate electrode and a second gate electrode over the first gate oxide film and the second gate oxide film, respectively, wherein after the formation of the first and second gate electrodes, the silicon layer in the first area is thicker than the silicon layer in the second area.Type: GrantFiled: March 16, 2017Date of Patent: October 2, 2018Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Makoto Yasuda, Taiji Ema, Mitsuaki Hori, Kazushi Fujita
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Publication number: 20170263606Abstract: A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.Type: ApplicationFiled: May 25, 2017Publication date: September 14, 2017Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kazushi Fujita, Taiji Ema, Mitsuaki Hori, Yasunobu Torii
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Patent number: 9748231Abstract: A semiconductor device includes: a substrate; a first active region formed in the substrate and that includes a first region that has a first width and a second region including a second width larger than the first width and extended in a first direction; a second active region formed in the substrate and extended in parallel to the second region of the first active region; and an element isolation insulating film formed in the substrate and that partitions the first active region and the second active region, respectively, wherein the second region of the first active region or the second active region includes a depressed part depressed in a second direction that is perpendicular to the first direction in a plan view.Type: GrantFiled: June 24, 2014Date of Patent: August 29, 2017Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Makoto Yasuda, Taiji Ema, Mitsuaki Hori, Kazushi Fujita
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Publication number: 20170186649Abstract: A semiconductor device manufacturing method includes forming a silicon layer by epitaxial growth over a semiconductor substrate having a first area and a second area; forming a first gate oxide film by oxidizing the silicon layer; removing the first gate oxide film from the second area, while maintaining the first gate oxide film in the first area; thereafter, increasing a thickness of the first gate oxide film in the first area and simultaneously forming a second gate oxide film by oxidizing the silicon layer in the second area; and forming a first gate electrode and a second gate electrode over the first gate oxide film and the second gate oxide film, respectively, wherein after the formation of the first and second gate electrodes, the silicon layer in the first area is thicker than the silicon layer in the second area.Type: ApplicationFiled: March 16, 2017Publication date: June 29, 2017Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Makoto Yasuda, Taiji Ema, Mitsuaki Hori, Kazushi Fujita
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Patent number: 9691767Abstract: A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.Type: GrantFiled: August 20, 2015Date of Patent: June 27, 2017Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kazushi Fujita, Taiji Ema, Mitsuaki Hori, Yasunobu Torii
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Patent number: 9685442Abstract: A semiconductor device including an insulating film in a first region of a semiconductor substrate; a first impurity region and a second impurity region of a first conductivity type, each of the regions including a part located deeper than the insulating film in contact with each other, and the insulating film being sandwiched by the first and second impurity regions in planar view in the first region of the semiconductor substrate; a metal silicide film on the first impurity region and in Schottky junction with the first impurity region; a first impurity of the first impurity region having a peak of a concentration profile deeper than a bottom of the insulating film; a second impurity of the second impurity region having a concentration higher than a concentration of the first impurity in a part of the first impurity region shallower than the bottom of the insulating film.Type: GrantFiled: October 16, 2015Date of Patent: June 20, 2017Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kazushi Fujita, Taiji Ema, Makoto Yasuda, Mitsuaki Hori
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Patent number: 9634021Abstract: A semiconductor device manufacturing method includes forming a silicon layer by epitaxial growth over a semiconductor substrate having a first area and a second area; forming a first gate oxide film by oxidizing the silicon layer; removing the first gate oxide film from the second area, while maintaining the first gate oxide film in the first area; thereafter, increasing a thickness of the first gate oxide film in the first area and simultaneously forming a second gate oxide film by oxidizing the silicon layer in the second area; and forming a first gate electrode and a second gate electrode over the first gate oxide film and the second gate oxide film, respectively, wherein after the formation of the first and second gate electrodes, the silicon layer in the first area is thicker than the silicon layer in the second area.Type: GrantFiled: June 9, 2015Date of Patent: April 25, 2017Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Makoto Yasuda, Taiji Ema, Mitsuaki Hori, Kazushi Fujita
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Patent number: 9431285Abstract: A method of manufacturing a semiconductor device including performing a first thermal processing a silicon substrate in a first atmosphere and at a first temperature to remove an oxide film above a surface of the silicon substrate, and after the first thermal processing, performing a second thermal processing the silicon substrate in a second atmosphere containing hydrogen and at a second temperature lower than the first temperature to terminate the surface of the silicon substrate with hydrogen.Type: GrantFiled: November 30, 2012Date of Patent: August 30, 2016Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Naoyoshi Tamura, Keita Nishigaya, Mitsuaki Hori, Hiroe Kawamura
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Publication number: 20160218103Abstract: It is therefore an object of the present invention to provide a method in which, in a semiconductor integrated circuit device, a plurality of transistors having wide-rangingly different Ioff levels are embedded together in a semiconductor device including transistors each using a non-doped channel. By controlling an effective channel length, a leakage current is controlled without changing an impurity concentration distribution in a transistor including a non-doped channel layer and a screen layer provided immediately under the non-doped channel layer.Type: ApplicationFiled: April 6, 2016Publication date: July 28, 2016Inventors: Taiji Ema, Kazushi Fujita, Yasunobu Torii, Mitsuaki Hori
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Patent number: 9390960Abstract: A method of manufacturing a semiconductor device including performing a first thermal processing a silicon substrate in a first atmosphere and at a first temperature to remove an oxide film above a surface of the silicon substrate, and after the first thermal processing, performing a second thermal processing the silicon substrate in a second atmosphere containing hydrogen and at a second temperature lower than the first temperature to terminate the surface of the silicon substrate with hydrogen.Type: GrantFiled: November 30, 2012Date of Patent: July 12, 2016Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Naoyoshi Tamura, Keita Nishigaya, Mitsuaki Hori, Hiroe Kawamura
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Publication number: 20160148932Abstract: A semiconductor device including an insulating film in a first region of a semiconductor substrate; a first impurity region and a second impurity region of a first conductivity type, each of the regions including a part located deeper than the insulating film in contact with each other, and the insulating film being sandwiched by the first and second impurity regions in planar view in the first region of the semiconductor substrate; a metal silicide film on the first impurity region and in Schottky junction with the first impurity region; a first impurity of the first impurity region having a peak of a concentration profile deeper than a bottom of the insulating film; a second impurity of the second impurity region having a concentration higher than a concentration of the first impurity in a part of the first impurity region shallower than the bottom of the insulating film.Type: ApplicationFiled: October 16, 2015Publication date: May 26, 2016Inventors: Kazushi Fujita, Taiji Ema, Makoto Yasuda, Mitsuaki Hori
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Publication number: 20150364484Abstract: A semiconductor device manufacturing method includes forming a silicon layer by epitaxial growth over a semiconductor substrate having a first area and a second area; forming a first gate oxide film by oxidizing the silicon layer; removing the first gate oxide film from the second area, while maintaining the first gate oxide film in the first area; thereafter, increasing a thickness of the first gate oxide film in the first area and simultaneously forming a second gate oxide film by oxidizing the silicon layer in the second area; and forming a first gate electrode and a second gate electrode over the first gate oxide film and the second gate oxide film, respectively, wherein after the formation of the first and second gate electrodes, the silicon layer in the first area is thicker than the silicon layer in the second area.Type: ApplicationFiled: June 9, 2015Publication date: December 17, 2015Inventors: Makoto Yasuda, Taiji Ema, Mitsuaki Hori, Kazushi Fujita
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Publication number: 20150357330Abstract: A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.Type: ApplicationFiled: August 20, 2015Publication date: December 10, 2015Inventors: Kazushi Fujita, Taiji Ema, Mitsuaki Hori, Yasunobu Torii
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Patent number: 9153501Abstract: A method for manufacturing a semiconductor device includes implanting indium into a first region of a semiconductor substrate; forming a first gate insulation film having a first film thickness in the first region and a second region different from the first region after the implanting; removing the first gate insulation film from the first region; applying heat treatment to the semiconductor substrate after the forming; and forming a second gate insulation film having a second film thickness on the first region after the applying. In the method, a temperature falling rate of the heat treatment in the applying is 20° C. per second or higher.Type: GrantFiled: June 14, 2011Date of Patent: October 6, 2015Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Mitsuaki Hori, Kazutaka Yoshizawa
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Patent number: 9147744Abstract: A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.Type: GrantFiled: July 3, 2013Date of Patent: September 29, 2015Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kazushi Fujita, Taiji Ema, Mitsuaki Hori, Yasunobu Torii
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Patent number: 8980710Abstract: An impurity layer is formed in a first region of a semiconductor substrate, a silicon layer is grown on the semiconductor substrate, a tunnel gate insulating film is formed on a first silicon layer of a second region, a first conductor layer is formed on the tunnel gate insulating film, a first silicon oxide film and a silicon nitride film are formed on a second silicon layer, in a reduced pressure state, oxygen and hydrogen are independently introduced into an oxidation furnace to expose the silicon nitride film to active species of the oxygen and active species of the hydrogen to thereby oxidize the silicon nitride film to form a second silicon oxide film, a gate insulating film is formed on the silicon layer of the first region, a second conductor layer is formed on the second silicon oxide film and on the gate insulating film, the second conductor layer and the first conductor layer of the second region are patterned to form a stack gate of a nonvolatile memory transistor, and the second conductor layer aType: GrantFiled: May 30, 2014Date of Patent: March 17, 2015Assignee: Fujitsu Semiconductor LimitedInventors: Taiji Ema, Mitsuaki Hori, Kazushi Fujita, Makoto Yasuda, Katsuaki Ookoshi
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Publication number: 20150008526Abstract: A semiconductor device includes: a substrate; a first active region formed in the substrate and that includes a first region that has a first width and a second region including a second width larger than the first width and extended in a first direction; a second active region formed in the substrate and extended in parallel to the second region of the first active region; and an element isolation insulating film formed in the substrate and that partitions the first active region and the second active region, respectively, wherein the second region of the first active region or the second active region includes a depressed part depressed in a second direction that is perpendicular to the first direction in a plan view.Type: ApplicationFiled: June 24, 2014Publication date: January 8, 2015Inventors: Makoto Yasuda, Taiji Ema, Mitsuaki Hori, Kazushi Fujita
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Publication number: 20140377921Abstract: An impurity layer is formed in a first region of a semiconductor substrate, a silicon layer is grown on the semiconductor substrate, a tunnel gate insulating film is formed on a first silicon layer of a second region, a first conductor layer is formed on the tunnel gate insulating film, a first silicon oxide film and a silicon nitride film are formed on a second silicon layer, in a reduced pressure state, oxygen and hydrogen are independently introduced into an oxidation furnace to expose the silicon nitride film to active species of the oxygen and active species of the hydrogen to thereby oxidize the silicon nitride film to form a second silicon oxide film, a gate insulating film is formed on the silicon layer of the first region, a second conductor layer is formed on the second silicon oxide film and on the gate insulating film, the second conductor layer and the first conductor layer of the second region are patterned to form a stack gate of a nonvolatile memory transistor, and the second conductor layer aType: ApplicationFiled: May 30, 2014Publication date: December 25, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiji Ema, Mitsuaki Hori, Kazushi Fujita, Makoto Yasuda, Katsuaki Ookoshi
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Patent number: 8778786Abstract: Silicon loss prevention in a substrate during transistor device element manufacture is achieved by limiting a number of photoresist mask and chemical oxide layer stripping opportunities during the fabrication process. This can be achieved through the use of a protective layer that remains on the substrate during formation and stripping of photoresist masks used in identifying the implant areas into the substrate. In addition, undesirable reworking steps due to photoresist mask misalignment are eliminated or otherwise have no effect on consuming silicon from the substrate during fabrication of device elements. In this manner, device elements with the same operating characteristics and performance can be consistently made from lot to lot.Type: GrantFiled: May 29, 2012Date of Patent: July 15, 2014Assignee: SuVolta, Inc.Inventors: Lance Scudder, Pushkar Ranade, Dalong Zhao, Teymur Bakhishev, Urupattur C. Sridharan, Taiji Ema, Toshifumi Mori, Mitsuaki Hori, Junji Oh, Kazushi Fujita, Yasunobu Torii