Patents by Inventor Mitsuaki Izuha
Mitsuaki Izuha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8691601Abstract: Disclosed herein is a semiconductor device, including: a semiconductor substrate; an integrated circuit formed on a first main surface of the semiconductor substrate; a penetrating electrode that penetrates the semiconductor substrate in the thickness direction and has its one end electrically connected to the integrated circuit; a bump electrode formed on a second main surface of the semiconductor substrate and electrically connected to another end of the penetrating electrode; and a test pad electrode formed on the second main surface of the semiconductor substrate and electrically connected to the bump electrode.Type: GrantFiled: December 15, 2010Date of Patent: April 8, 2014Assignee: Sony CorporationInventor: Mitsuaki Izuha
-
Patent number: 8497205Abstract: In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.Type: GrantFiled: December 29, 2011Date of Patent: July 30, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kyoichi Suguro, Mitsuaki Izuha
-
Publication number: 20120164811Abstract: In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.Type: ApplicationFiled: December 29, 2011Publication date: June 28, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Kyoichi Suguro, Mitsuaki Izuha
-
Publication number: 20110204357Abstract: Disclosed herein is a semiconductor device, including: a semiconductor substrate; an integrated circuit formed on a first main surface of the semiconductor substrate; a penetrating electrode that penetrates the semiconductor substrate in the thickness direction and has its one end electrically connected to the integrated circuit; a bump electrode formed on a second main surface of the semiconductor substrate and electrically connected to another end of the penetrating electrode; and a test pad electrode formed on the second main surface of the semiconductor substrate and electrically connected to the bump electrode.Type: ApplicationFiled: December 15, 2010Publication date: August 25, 2011Applicant: Sony CorporationInventor: Mitsuaki Izuha
-
Patent number: 7879723Abstract: In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.Type: GrantFiled: January 30, 2009Date of Patent: February 1, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kyoichi Suguro, Mitsuaki Izuha
-
Publication number: 20090203181Abstract: In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a silicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.Type: ApplicationFiled: January 30, 2009Publication date: August 13, 2009Inventors: Kyoichi Suguro, Mitsuaki Izuha
-
Publication number: 20060160315Abstract: In an embodiment of the present invention, a semiconductor layer having regions into which a p-type impurity, an n-type impurity and a (p+n) impurity are respectively introduced is formed as a surface layer by being heat-treated. An impurity segregation layer on these regions is removed, and a film of a metallic material is thereafter formed on the regions and is heat-treated, thereby forming a suicide film on the semiconductor layer. In another embodiment, an impurity is introduced into the impurity segregation layer, and a film of a metallic material is thereafter formed on the impurity segregation layer and is heat-treated to form a silicide film.Type: ApplicationFiled: December 28, 2005Publication date: July 20, 2006Inventors: Kyoichi Suguro, Mitsuaki Izuha
-
Patent number: 6924518Abstract: There is disclosed is a semiconductor device which comprises a semiconductor substrate, isolation regions formed within the semiconductor substrate to define the active region, a pair of impurity diffusion regions formed within the element region in a manner to have surfaces elevated from the isolation region, a SiGe film formed on an upper surface of the impurity diffusion region so as to cover partly the side surface of the impurity diffusion region, a Ge concentration in the SiGe film being higher at a lower surface of the SiGe film than at an upper surface of the SiGe film, a metal silicide layer formed on the SiGe film, and a gate electrode formed in the active region of the semiconductor substrate with a gate insulating film interposed therebetween and having a sidewall insulating film formed on the side surface.Type: GrantFiled: December 23, 2003Date of Patent: August 2, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Toshihiko Iinuma, Ichiro Mizushima, Mitsuaki Izuha, Kiyotaka Miyano, Kyoichi Suguro
-
Publication number: 20050006637Abstract: There is disclosed is a semiconductor device which comprises a semiconductor substrate, isolation regions formed within the semiconductor substrate to define the active region, a pair of impurity diffusion regions formed within the element region in a manner to have surfaces elevated from the isolation region, a SiGe film formed on an upper surface of the impurity diffusion region so as to cover partly the side surface of the impurity diffusion region, a Ge concentration in the SiGe film being higher at a lower surface of the SiGe film than at an upper surface of the SiGe film, a metal silicide layer formed on the SiGe film, and a gate electrode formed in the active region of the semiconductor substrate with a gate insulating film interposed therebetween and having a sidewall insulating film formed on the side surface.Type: ApplicationFiled: December 23, 2003Publication date: January 13, 2005Inventors: Toshihiko Iinuma, Ichiro Mizushima, Mitsuaki Izuha, Kiyotaka Miyano, Kyoichi Suguro
-
Publication number: 20040113209Abstract: A semiconductor device has a MOSFET. The MOSFET includes source and drain regions, a gate insulating film, a gate electrode, and first, second, and third metal silicide films. The source and drain regions are formed in the major surface region of a semiconductor substrate. The gate insulating film is formed on the channel region between the source and drain regions. The gate electrode is formed on the gate insulating film and includes a poly-Si1−xGex layer having a Ge/(Si+Ge) composition ratio x (0<x<0.2). The first metal silicide film is formed on the gate electrode and made of NiSi1−yGey. The second and third metal silicide films are formed on the source and drain regions, respectively, and made of NiSi.Type: ApplicationFiled: September 12, 2003Publication date: June 17, 2004Inventors: Mitsuaki Izuha, Toshihiko Iinuma, Kyoichi Suguro
-
Patent number: 6060735Abstract: A thin film dielectric device is disclosed, that comprises a substrate, a lower electrode formed on the substrate and composed of a laminate film having columnar grains that have grown in a vertical to a surface of the substrate, a dielectric thin film formed on the lower electrode and composed of a perovskite oxide, the dielectric thin film being a polycrystalline film having columnar grains that have successively grown from the columnar grains of the lower electrode and that takes over a crystal orientation of the lower electrode, the lattice constant of the lower electrode being matched with the lattice constant of the dielectric thin film at the interface therebetween with the columnar grains, and an upper electrode formed on the dielectric thin film. The lattice matching of the columnar grains solves problems of the increase of the leak current of the thin film dielectric device and the degradation of the dielectric breakdown resistance.Type: GrantFiled: September 4, 1997Date of Patent: May 9, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuaki Izuha, Noburu Fukushima, Kazuhide Abe
-
Patent number: 5889299Abstract: A thin film capacitor including a first electrode having on its surface a (100) face of cubic system or a (001) face of tetragonal system, a dielectric thin film epitaxially grown on the first electrode and exhibiting a crystal structure which inherently belongs to a perovskite structure of cubic system, and a second electrode formed on the dielectric thin film. Further, the dielectric thin film meets the following relationship V/V.sub.0 .gtoreq.1.01 where a unit lattice volume of true perovskite crystal structure belonging to the cubic system (lattice constant a.sub.0) is represented by V.sub.0 =a.sub.0.sup.3, and a unit lattice volume (lattice constant a=b.noteq.c) which is strained toward a tetragonal system after the epitaxial growth is represented by V=a.sup.2 c, and also meets the following relationship c/a.gtoreq.1.01 where c/a represents a ratio between a lattice constant "c" in the direction thicknesswise of the film and a lattice constant "a" in the direction parallel with a plane of the film.Type: GrantFiled: February 21, 1997Date of Patent: March 30, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhide Abe, Shuichi Komatsu, Mitsuaki Izuha, Noburu Fukushima, Kenya Sano, Takashi Kawakubo