Abstract: An aspect of the invention provides a solar cell that comprises a semiconductor substrate having a light-receiving surface and a rear surface; a first semiconductor layer having a first conductivity type; a second semiconductor layer having a second conductivity type, the first semiconductor layer and the second semiconductor layer being formed on the rear surface, and a trench formed in the rear surface, wherein the first semiconductor layer is formed on the rear surface in which the trench is not formed, and the second semiconductor layer is formed on a side surface of the trench in an arrangement direction in which the first semiconductor layer and the second semiconductor layer are alternately arranged and on a bottom surface of the trench.

Abstract: A method of manufacturing a solar cell includes: forming a solar cell substrate having one main surface and the other main surface and having a p-type surface and an n-type surface which are exposed on one region and another region in the one main surface, respectively; forming seed layers in an electrically separated state on the p-type surface and the n-type surface, respectively; and forming a plated film on the seed layer on each of the p-type surface and the n-type surface by an electrolytic plating method.

Abstract: A solar cell manufacturing method includes: forming a first amorphous semiconductor layer of one conductivity type on a main surface of a semiconductor substrate; forming an insulation layer on the first amorphous semiconductor layer; etching to remove the insulation layer and the first amorphous semiconductor layer in a predetermined first region; forming a second amorphous semiconductor layer of an other conductivity type on the insulation layer after the etching, the other conductivity type being different from the one conductivity type; and etching to remove the second amorphous semiconductor layer in a predetermined second region, wherein the etching to remove the insulation layer and the first amorphous semiconductor layer in a predetermined first region includes: applying an etching paste to the insulation layer in the predetermined first region; and etching to remove the insulation layer and the first amorphous semiconductor layer in the predetermined first region using the etching paste.

Abstract: A solar cell includes a solar cell substrate including a principal surface on which a p-type surface and an n-type surface are exposed, a p-side electrode formed on the p-type surface and including a first linear portion linearly extending in a first direction, and an n-side electrode formed on the n-type surface and including a second linear portion linearly extending in the first direction and arranged next to the first linear portion in a second direction orthogonal to the first direction. Corners of a tip end of at least one of the first and second linear portions are formed in a chamfered shape.

Abstract: Disclosed is a solar cell that comprises a photoelectric conversion body, a first electrode including a first finger portion that is placed on one main surface of the photoelectric conversion body and extends in first direction, a second electrode including a second finger portion which is placed on the one main surface of the photoelectric conversion body to be adjacent to the first finger portion in second direction intersecting the first direction and extends in the first direction, a first insulating layer covering at least part of a tip end portion of the first finger portion, which tip end portion is located on first side in the first direction, and a second insulating layer covering at least part of a tip end portion of the second finger portion, which tip end portion is located on a second side in the first direction.

Abstract: A solar cell manufacturing method includes: forming a first amorphous semiconductor layer of one conductivity type on a main surface of a semiconductor substrate; forming an insulation layer on the first amorphous semiconductor layer; etching to remove the insulation layer and the first amorphous semiconductor layer in a predetermined first region; forming a second amorphous semiconductor layer of an other conductivity type on the insulation layer after the etching, the other conductivity type being different from the one conductivity type; and etching to remove the second amorphous semiconductor layer in a predetermined second region, wherein the etching to remove the insulation layer and the first amorphous semiconductor layer in a predetermined first region includes: applying an etching paste to the insulation layer in the predetermined first region; and etching to remove the insulation layer and the first amorphous semiconductor layer in the predetermined first region using the etching paste.

Abstract: A solar cell module is provided with a plurality of solar cells and a wiring material. Each solar cell includes a p-side electrode and an n-side electrode arranged on one principal surface thereof. For each pair of adjacent solar cells, the wiring material electrically connects the p-side electrode of one solar cell and the n-side electrode of the other solar cell. Surface layers of the p-side electrodes and the n-side electrodes comprises, respectively, plating layers each containing at least one power-supplied point. The wiring material is bonded to the solar cells at regions each of which at least includes the power-supplied point.

Abstract: A solar cell includes semiconductor substrate of a first conductivity type; first semiconductor layer having a first conductivity type; second semiconductor layer having a second conductivity type; first electrode; second electrode; and insulating layer. First semiconductor layer and second semiconductor layer are formed on rear surface. When one end portion of insulating layer which is formed on first semiconductor layer and which is on a side close to first electrode is defined as first insulating-layer end portion and another end portion of insulating layer on a side close to second electrode is defined as second insulating-layer end portion in arrangement direction x, a distance from end point of second-semiconductor-layer end portion in contact with rear surface to second insulating-layer end portion in arrangement direction x is shorter than a distance from end point to first insulating-layer end portion in arrangement direction x.

Abstract: A solar cell includes a solar cell substrate including a principal surface on which a p-type surface and an n-type surface are exposed, a p-side electrode formed on the p-type surface and including a first linear portion linearly extending in a first direction, and an n-side electrode formed on the n-type surface and including a second linear portion linearly extending in the first direction and arranged next to the first linear portion in a second direction orthogonal to the first direction. Corners of a tip end of at least one of the first and second linear portions are formed in a chamfered shape.

Abstract: Disclosed is a solar cell that comprises a photoelectric conversion body, a first electrode including a first finger portion that is placed on one main surface of the photoelectric conversion body and extends in first direction, a second electrode including a second finger portion which is placed on the one main surface of the photoelectric conversion body to be adjacent to the first finger portion in second direction intersecting the first direction and extends in the first direction, a first insulating layer covering at least part of a tip end portion of the first finger portion, which tip end portion is located on first side in the first direction, and a second insulating layer covering at least part of a tip end portion of the second finger portion, which tip end portion is located on a second side in the first direction.

Abstract: A solar cell includes a photoelectric conversion body including one principal surface provided with a p-type surface and an n-type surface, a p-side electrode disposed on the p-type surface, an n-side electrode disposed on the n-type surface, and an insulating layer disposed between the p-side electrode and the n-side electrode and including a convex shaped surface.

Abstract: A semiconductor device includes a substrate made of a semiconductor material, an n-type semiconductor layer arranged on a portion of one principal surface of the substrate, and a p-type semiconductor layer arranged on a portion of the one principal surface of the substrate, the portion not provided with the n-type semiconductor layer. The n-type semiconductor layer includes a portion located right above the p-type semiconductor layer.

Abstract: A solar cell includes semiconductor substrate of a first conductivity type; first semiconductor layer having a first conductivity type; second semiconductor layer having a second conductivity type; first electrode; second electrode; and insulating layer. First semiconductor layer and second semiconductor layer are formed on rear surface. When one end portion of insulating layer which is formed on first semiconductor layer and which is on a side close to first electrode is defined as first insulating-layer end portion and another end portion of insulating layer on a side close to second electrode is defined as second insulating-layer end portion in arrangement direction x, a distance from end point of second-semiconductor-layer end portion in contact with rear surface to second insulating-layer end portion in arrangement direction x is shorter than a distance from end point to first insulating-layer end portion in arrangement direction x.

Abstract: An aspect of the invention provides a solar cell that comprises a semiconductor substrate having a light-receiving surface and a rear surface; a first semiconductor layer having a first conductivity type; a second semiconductor layer having a second conductivity type, the first semiconductor layer and the second semiconductor layer being formed on the rear surface, and a trench formed in the rear surface, wherein the first semiconductor layer is formed on the rear surface in which the trench is not formed, and the second semiconductor layer is formed on a side surface of the trench in an arrangement direction in which the first semiconductor layer and the second semiconductor layer are alternately arranged and on a bottom surface of the trench.

Abstract: A wiring structure includes a first wiring, a first interlayer dielectric film having a first opening, a second wiring formed with a first recess portion on a region corresponding to the first opening, a second interlayer dielectric film having a second opening and a third wiring so formed as to cover the second interlayer dielectric film, wherein an inner side surface of the second opening is arranged on a region corresponding to the first recess portion and formed such that an opening width of a portion in the vicinity of an upper end increases from a lower portion toward an upper portion.

Abstract: A wiring structure includes a first wiring, a first interlayer dielectric film having a first opening, a second wiring formed with a first recess portion on a region corresponding to the first opening, a second interlayer dielectric film having a second opening and a third wiring so formed as to cover the second interlayer dielectric film, wherein an inner side surface of the second opening is arranged on a region corresponding to the first recess portion and formed such that an opening width of a portion in the vicinity of an upper end increases from a lower portion toward an upper portion.

Abstract: A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which include sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer, are formed in a semiconductor element formation region. A planar wiring layer is embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.

Abstract: A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which include sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer, are formed in a semiconductor element formation region. A planar wiring layer is embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.

Abstract: In accordance with a proposed resist pattern forming method, contact angles between the surface of a resist and a rinse is adjusted within a predetermined range, a volatil surfactant which does not remain by drying is mixed in the rinse so as to reduce a surface tension, the rinse is dried under a critical condition of the rinse in order not to cause the surface tension to exert. The occurrence of an attractive force between the resist patterns may be thereby weakened or nullified, so that falling of the patterns can be effectively prevented which very often happened at forming fine resist patterns or resist patterns of high aspect. On the other hand, depending upon structure of said resist pattern, it is possible to effectively prevent outermost main patterns of gathering resist patterns from falling down. By providing such effects, yieldings of products are increased. Further, the present invention may be also applied to a lithography illumination sources of which are light, electron, X-ray, ion beam, etc.

Abstract: In accordance with a proposed resist pattern forming method, contact angles between the surface of a resist and a rinse is adjusted within a predetermined range, a volatil surfactant which does not remain by drying is mixed in the rinse so as to reduce a surface tension, the rinse is dried under a critical condition of the rinse in order not to cause the surface tension to exert. The occurrence of an attractive force between the resist patterns may be thereby weakened or nullified, so that falling of the patterns can be effectively prevented which very often happened at forming fine resist patterns or resist patterns of high aspect. On the other hand, depending upon structure of said resist pattern, it is possible to effectively prevent outermost main patterns of gathering resist patterns from falling down. By providing such effects, yielding of products are increased. Further, the present invention may be also applied to a lithography illumination sources of which are light, electron, X-ray, ion beam, etc.