Abstract: In a layout method for an LSI having a plurality of cells, automated arrangement of cells is performed on the basis of a netlist, which has cells and connection data therefor, and timing conditions, and, once a timing optimization processing is performed so that a plurality of cells are arranged on a chip, global wiring processing is implemented and the wiring congestion rate is analyzed. In addition, in small regions where a wiring congestion rate is so high that detailed wiring processing is judged to be difficult, cell rearrangement processing is implemented. Next, detailed wiring processing is performed with respect to the cells which have been rearranged. The rearrangement of cells is performed only in small regions with a high congestion rate, with the result that the overall cell arrangement in which timing is optimized is not changed markedly, whereby it is possible to reduce the probability of wiring being impossible in the course of the detailed wiring processing.

Abstract: Each binary carry logic circuit 20 of half adder circuits other than that for the least significant digit comprises a transfer gate 212 turned on when an input bit A2 is active and receiving a carry-in bit *C2 at its data input, and a transistor 23, turned on when the input bit A2 is inactive, connected between a power supply potential VDD and the data output of the transfer gate 212 a signal on which is a carry-out bit *C3. Transfer gates 212 to 214 of binary carry logic circuits other than that for the least significant digit are connected in chain, and are simultaneously on/off controlled by input bits A2 to A4, letting the carry-in bit *C2 from the least significant digit propagate through the transfer gate chain at a high speed.

Abstract: Disclosed is a method for automatic wiring design between block circuits of an integrated circuit, which performs an automatic connection between an inter-block wire disposed between a first circuit block and a second circuit block, and terminals formed along sides of the first and second blocks, the sides facing each other. The method comprises the steps of (S2) sorting the terminals according to the width thereof; and (S3˜S11) selecting a terminal from the terminals in descending order of the width, and connecting between the selected terminal and an inter-block wire belonging to a same net as the terminal.

Abstract: Disclosed is a method for automatic wiring design between block circuits of an integrated circuit, which performs an automatic connection between an inter-block wire disposed between a first circuit block and a second circuit block, and terminals formed along sides of the first and second blocks, the sides facing each other. The method comprises the steps of (S2) sorting the terminals according to the width thereof; and (S3˜S11) selecting a terminal from the terminals in descending order of the width, and connecting between the selected terminal and an inter-block wire belonging to a same net as the terminal.

Abstract: In a layout method for an LSI having a plurality of cells, automated arrangement of cells is performed on the basis of a netlist, which has cells and connection data therefor, and timing conditions, and, once a timing optimization processing is performed so that a plurality of cells are arranged on a chip, global wiring processing is implemented and the wiring congestion rate is analyzed. In addition, in small regions where a wiring congestion rate is so high that detailed wiring processing is judged to be difficult, cell rearrangement processing is implemented. Next, detailed wiring processing is performed with respect to the cells which have been rearranged. The rearrangement of cells is performed only in small regions with a high congestion rate, with the result that the overall cell arrangement in which timing is optimized is not changed markedly, whereby it is possible to reduce the probability of wiring being impossible in the course of the detailed wiring processing.

Abstract: Each binary carry logic circuit 20 of half adder circuits other than that for the least significant digit comprises a transfer gate 212 turned on when an input bit A2 is active and receiving a carry-in bit *C2 at its data input, and a transistor 23, turned on when the input bit A2 is inactive, connected between a power supply potential VDD and the data output of the transfer gate 212 a signal on which is a carry-out bit *C3. Transfer gates 212 to 214 of binary carry logic circuits other than that for the least significant digit are connected in chain, and are simultaneously on/off controlled by input bits A2 to A4, letting the carry-in bit *C2 from the least significant digit propagate through the transfer gate chain at a high speed.

Abstract: A method of designing a semiconductor integrated circuit includes the steps of generating a cell that includes a flip-flop and backup transistors, designing a circuit by use of the cell, and adjusting a timing by connecting the backup transistors to the flip-flop if there is a need to adjust timing of the flip-flop.

Abstract: A method of manufacturing a semiconductor device, including the steps of: cooling a semiconductor wafer to a predetermined temperature, the semiconductor wafer being mounted on a stage provided with cooling means and having a thin oxide film on a surface thereof; supplying energy to gas containing hydrogen and water vapor to excite the gas into a plasma state; adding nitrogen fluoride downstream into a flow of the gas in the plasma state; and introducing a flow of the gas, including the nitrogen fluoride, to the semiconductor wafer to etch the thin oxide film while maintaining the semiconductor wafer at the predetermined temperature.

Abstract: Novel ergoline derivatives and acid addition salts thereof are disclosed. These ergoline derivatives possess excellent anti-hypertensive activity, vasodilating activity, anti-ulcer activity, gastric secretion inhibitory activity, brain metabolism improving activity, anti-depressive activity and dopamine-like activity, and, therefore, are useful for prevention and treatment of various diseases such as hypertension, a wide variety of vein disorders, peptic ulcer, brain absormality, depression, Parkinson's disease, high prolactin blood disease, etc.

Abstract: Novel pyridine compounds and the pharmaceutically acceptable salts thereof having a specific inhibitory activity on thromboxane A.sub.2 biosynthesis in mammals useful for prevention and treatment of various disorders caused by thromboxane A.sub.2, for example, thrombosis, cardiac infarction, diabetic vascular complications, asthma, etc. are disclosed.

Abstract: Novel 1(2H)-isoquinolone compounds and the acid addition salts thereof are disclosed. These compounds are useful as pharmaceutical agents in view of their anti-ulcer, stomach mucous membrane blood flow increasing, anti-hypertensive, analgesic, anti-histamine, anti-cholinergic and gastric secretion inhibitory activities.

Abstract: A flavan compound represented by the formula (I) ##STR1## wherein R, R.sub.1, R.sub.2 and R.sub.3 are as defined above, and the pharmaceutically acceptable acid addition salt thereof, which are useful as pharmaceutical agent having anti-convulsive, anti-ulcer, anti-arrythmic and diuretic activities.

Abstract: Cis or trans-1,5-benzothiazepine compounds represented by the formula (I): ##STR1## wherein R.sub.1 represents a hydrogen atom, a halogen atom, an alkyl group or an alkoxy group and R.sub.2 represents a hydrogen atom, an alkyl group or a hydroxyalkyl group and the pharmaceutically acceptable acid addition salts and quaternary ammonium salts thereof which exhibit anticholinergic activity and are useful as anti-ulcer, gastric secretion inhibiting and antispasmodic agents in mammals, and a process for preparing the same.

Abstract: Pyrazole derivatives represented by the formula ##SPC1##Wherein R, X, R.sub.2 and R.sub.3 are hereinafter defined, which are useful as analgesics and anti-inflammatory agents and a process for preparing the pyrazole derivatives are disclosed.