Patents by Inventor Mitsuaki Tomida

Mitsuaki Tomida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7646221
    Abstract: A buffer circuit permitting an input signal to pass and prohibiting the input signal from passing corresponding to an output control signal, including an output switching device, a control portion having a first switching circuit controlling the output switching device into conductive state and a second switching circuit controlling the output switching device into non-conductive state, and controlling the output switching device into the conductive state or non-conductive state corresponding to the input signal and the output control signal, wherein a connecting point between the first switching circuit and the second switching circuit is coupled to the output switching device, and a changing portion connected to the second switching circuit in series and limiting the drive capacity of the output switching device when the output control signal is in an output prohibition state of prohibiting the input signal from passing.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: January 12, 2010
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Toyoki Suzuki, Mitsuaki Tomida, Shuuichi Nagaya
  • Patent number: 7501852
    Abstract: A tolerant input circuit that functions stably regardless of fabrication differences without having to adjust the threshold value of an input circuit. The tolerant input circuit includes a step-down device configured by an N-channel MOS transistor connected between an input pad and the input circuit. Voltage from a power supply is supplied to the gate of the N-channel MOS transistor in the step-down device to decrease the voltage of a high voltage signal provided to the input pad to the voltage of the power supply or lower. The signal with decreased voltage is provided to the input circuit. The tolerant input circuit includes a back gate voltage control circuit for increasing back gate voltage of the N-channel MOS transistor in the step-down device when the input pad is provided with a high voltage signal.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: March 10, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventors: Toyoki Suzuki, Mitsuaki Tomida, Masahiro Iwamoto, Osamu Uno
  • Publication number: 20080079475
    Abstract: A buffer circuit permitting an input signal to pass and prohibiting the input signal from passing corresponding to an output control signal, including an output switching device, a control portion having a first switching circuit controlling the output switching device into conductive state and a second switching circuit controlling the output switching device into non-conductive state, and controlling the output switching device into the conductive state or non-conductive state corresponding to the input signal and the output control signal, wherein a connecting point between the first switching circuit and the second switching circuit is coupled to the output switching device, and a changing portion connected to the second switching circuit in series and limiting the drive capacity of the output switching device when the output control signal is in an output prohibition state of prohibiting the input signal from passing.
    Type: Application
    Filed: September 24, 2007
    Publication date: April 3, 2008
    Inventors: Toyoki Suzuki, Mitsuaki Tomida, Shuuichi Nagaya
  • Publication number: 20060220686
    Abstract: A tolerant input circuit that functions stably regardless of fabrication differences without having to adjust the threshold value of an input circuit. The tolerant input circuit includes a step-down device configured by an N-channel MOS transistor connected between an input pad and the input circuit. Voltage from a power supply is supplied to the gate of the N-channel MOS transistor in the step-down device to decrease the voltage of a high voltage signal provided to the input pad to the voltage of the power supply or lower. The signal with decreased voltage is provided to the input circuit. The tolerant input circuit includes a back gate voltage control circuit for increasing back gate voltage of the N-channel MOS transistor in the step-down device when the input pad is provided with a high voltage signal.
    Type: Application
    Filed: September 27, 2005
    Publication date: October 5, 2006
    Inventors: Toyoki Suzuki, Mitsuaki Tomida, Masahiro Iwamoto, Osamu Uno