Abstract: A method for manufacturing a display device is provided in which an a-Si semiconductor layer including signal terminal regions is formed in an island manner and the total parasitic capacitance is minimized while the increase of the number of process steps for photolithography is restricted. Signal lines, signal lead wires, signal terminals, part of drain electrodes, and part of source electrodes are formed using thin portions of a resist pattern. Small regions each from the position where a drain electrode and a source electrode oppose each other to positions beyond the width of a gate electrode are formed using the thick portions of the resist pattern. The resist pattern having these portions is used as a mask to etch a metal layer and a contact layer, and is reflowed to form a reflowed resist mask. The reflowed resist mask is used to form semiconductor islands.

Abstract: A thin-film semiconductor device is provided including a plurality of thin-film transistors (TFT) having different driving voltages formed on an glass substrate, wherein a gate insulator electric field at each of the driving voltages of the plurality of thin-film transistors is in a range of about 1 MV/cm to 2 MV/cm, and a drain concentration of p-type thin-film transistors (TFT) is in a range of about 3E+19/cm3 to 1E+20/cm3.

Abstract: In a semiconductor device having an N-channel MOS transistor and a P-channel MOS transistor, each of the N-channel and P-channel MOS transistors is made up of a polycrystal silicon layer, a gate insulating film, and a gate electrode containing a gate polysilicon on a glass substrate. A method of manufacturing the semiconductor device includes the steps of injecting an impurity into the gate polysilicon at a same time as or in a different step of impurity injection at a time of formation of source/drains of the MOS transistors or formation of an LDD (Lightly Doped Drain), to make an N-type of a gate polysilicon in the N-channel MOS transistor and make a P-type of a gate polysilicon in the P-channel MOS transistor and, furthermore, setting a thickness of the polycrystal silicon layer less than the width of a depletion layer which occurs when an inversion channel is formed. Thus, fluctuations in values of threshold voltages of the MOS transistors are reduced to realize low-voltage driving.

Abstract: Prior to converting a non-single crystal material of a semiconductor film into a single crystal material through the use of a laser beam, at least one dopant is introduced into whole of the semiconductor film. Then, the non-single crystal semiconductor film is irradiated with a laser beam to crystallize the semiconductor film. In this case, a ratio between quasi-fermi level of the single crystal material within one of transistor formation regions used to form transistors of different conductivity types and quasi-fermi level of the single crystal material within the other thereof is made to be between 0.5:1 and 2.0:1. Thus, transistors of different conductivity types are formed in the crystallized semiconductor film.

Abstract: A method for manufacturing a thin film semiconductor device is provided which is capable of achieving simplification of manufacturing processes and of improving alignment accuracy without using a plurality of alignment masks. An alignment pattern is formed by using a resist layer having a plurality of regions each having a different film thickness corresponding to each of a plurality of patterns produced using a halftone mask having a halftone exposure region as a photomask and by forming a light transmitting portion to be an aperture pattern and by etching an underlying silicon layer. By having an underlying silicon layer exposed and implanting ions into an entire resist layer, only a main pattern region is doped with the ions.

Abstract: Prior to converting a non-single crystal material of a semiconductor film into a single crystal material through the use of a laser beam, at least one dopant is introduced into whole of the semiconductor film. Then, the non-single crystal semiconductor film is irradiated with a laser beam to crystallize the semiconductor film. In this case, a ratio between quasi-fermi level of the single crystal material within one of transistor formation regions used to form transistors of different conductivity types and quasi-fermi level of the single crystal material within the other thereof is made to be between 0.5:1 and 2.0:1. Thus, transistors of different conductivity types are formed in the crystallized semiconductor film.

Abstract: A method for manufacturing a thin film semiconductor device is provided which is capable of achieving simplification of manufacturing processes and of improving alignment accuracy without using a plurality of alignment masks. An alignment pattern is formed by using a resist layer having a plurality of regions each having a different film thickness corresponding to each of a plurality of patterns produced using a halftone mask having a halftone exposure region as a photomask and by forming a light transmitting portion to be an aperture pattern and by etching an underlying silicon layer. By having an underlying silicon layer exposed and implanting ions into an entire resist layer, only a main pattern region is doped with the ions.

Abstract: In a semiconductor device having an N-channel MOS transistor and a P-channel MOS transistor, each of the N-channel and P-channel MOS transistors is made up of a polycrystal silicon layer, a gate insulating film, and a gate electrode containing a gate polysilicon on a glass substrate. A method of manufacturing the semiconductor device includes the steps of injecting an impurity into the gate polysilicon at a same time as or in a different step of impurity injection at a time of formation of source/drains of the MOS transistors or formation of an LDD (Lightly Doped Drain), to make an N-type of a gate polysilicon in the N-channel MOS transistor and make a P-type of a gate polysilicon in the P-channel MOS transistor and, furthermore, setting a thickness of the polycrystal silicon layer less than the width of a depletion layer which occurs when an inversion channel is formed. Thus, fluctuations in values of threshold voltages of the MOS transistors are reduced to realize low-voltage driving.

Abstract: A thin-film semiconductor device is provided including a plurality of thin-film transistors (TFT) having different driving voltages formed on an glass substrate, wherein a gate electrode electric field at each of the driving voltages of the plurality of thin-film transistors is in a range of about 1MV/cm to 2MV/cm, and a drain concentration of p-type thin-film transistors (TFT) is in a range of about 3E+19/cm3 to 1E+20/cm3.

Abstract: Prior to converting a non-single crystal material of a semiconductor film into a single crystal material through the use of a laser beam, at least one dopant is introduced into whole of the semiconductor film. Then, the non-single crystal semiconductor film is irradiated with a laser beam to crystallize the semiconductor film. In this case, a ratio between quasi-fermi level of the single crystal material within one of transistor formation regions used to form transistors of different conductivity types and quasi-fermi level of the single crystal material within the other thereof is made to be between 0.5:1 and 2.0:1. Thus, transistors of different conductivity types are formed in the crystallized semiconductor film.

Abstract: A method for manufacturing a thin film semiconductor device is provided which is capable of achieving simplification of manufacturing processes and of improving alignment accuracy without using a plurality of alignment masks. An alignment pattern is formed by using a resist layer having a plurality of regions each having a different film thickness corresponding to each of a plurality of patterns produced using a halftone mask having a halftone exposure region as a photomask and by forming a light transmitting portion to be an aperture pattern and by etching an underlying silicon layer. By having an underlying silicon layer exposed and implanting ions into an entire resist layer, only a main pattern region is doped with the ions.

Abstract: In a semiconductor device having an N-channel MOS transistor and a P-channel MOS transistor, each of the N-channel and P-channel MOS transistors is made up of a polycrystal silicon layer, a gate insulating film, and a gate electrode containing a gate polysilicon on a glass substrate. A method of manufacturing the semiconductor device includes the steps of injecting an impurity into the gate polysilicon at a same time as or in a different step of impurity injection at a time of formation of source/drains of the MOS transistors or formation of an LDD (Lightly Doped Drain), to make an N-type of a gate polysilicon in the N-channel MOS transistor and make a P-type of a gate polysilicon in the P-channel MOS transistor and, furthermore, setting a thickness of the polycrystal silicon layer less than the width of a depletion layer which occurs when an inversion channel is formed. Thus, fluctuations in values of threshold voltages of the MOS transistors are reduced to realize low-voltage driving.

Abstract: In order to solve problems of a conventional level shift circuit which is difficult to use since a bias voltage is needed and where a number of P-channel MOSFETs is large and an area thereof is large, a level shift circuit comprises N-channel MOSFETs N1, N2 and N3 gates of which are respectively connected to input terminals 1, 2 and 3 and sources of which are commonly connected to a low potential side power source terminal, and P-channel MOSFETs P1, P2 and P3 sources of which are connected commonly to a high potential side power source terminal and drains of which are connected respectively to drains of the N-channel MOSFETs N1, N2 and N3. The P-channel MOSFETs P1 and P2 are provided with drain intermediate taps T1 and T2, the gate of the P-type MOSFET P1 is connected to the drain intermediate tap T2 of the P-channel MOSFET P2 and the gate of the P-channel MOSFET P2 is connected to the drain intermediate tap T1 of the P-channel MOSFET P1.

Abstract: A temperature detection circuit using a threshold voltage of a MOSFET with a further improved detection characteristic. The circuit has first and second lateral MOSFETs formed in a well region of a conductivity type which is formed on a surface of a semiconductor region of an opposite conductivity type, a first power source which drives the first lateral MOSFET at an operation point where a temperature has influence on a characteristic between a gate-source voltage and a drain current characteristic thereof, a second power source which drives the second lateral MOSFET at an operation point where the temperature has no influence on a characteristic between a gate-source voltage and a drain current characteristic thereof, and a comparator which compares a difference between outputs from the first and second lateral MOSFETs with a predetermined set value to detect the temperature.

Abstract: A power MOSFET includes a main MOSFET connected in series with a load resistor between a high voltage power supply voltage and ground, and a series circuit connected in parallel to the main MOSFET and composed of a sensing MOSFET and a converting MOSFET for converting a shunted current flowing through the sensing MOSFET into a detected voltage signal, which is supplied to one input of an operational amplifier. A gate of the main MOSFET and a gate of the sensing MOSFET are connected in common to an output of a gate drive circuit. The other input of the operational amplifier is connected to a reference voltage, so that the detected voltage signal is compared with the reference voltage. An output of the operational amplifier is fed back to the gate drive circuit, so that the gate drive circuit controls a gate voltage supplied to the gate of the main MOSFET and the gate of the sensing MOSFET, in order to prevent an overcurrent from flowing through the power MOSFET.

Abstract: A vertical field effect transistor comprises a MOSFET cell zone which is formed in a principal surface of an N-type semiconductor substrate and in which a plurality of MOSFET cells are formed and connected in parallel with one another. A gate electrode pad and a source electrode pad are formed in the principal surface of the semiconductor substrate, separately from the MOSFET cell zone. A drain electrode pad is formed on a rear surface of the semiconductor substrate. A plurality of diodes are formed in the principal surface of the semiconductor substrate and arranged to form at least one array of diodes along an outer periphery of the MOSFET cell zone. An N-type region of each of the diodes is formed of the N-type semiconductor substrate itself and a P-type region of each of the diodes is connected to an electrode which is connected to a source electrode of the MOSFET cells.

Abstract: The present invention provides a MOS field effect transistor comprising: a semiconductor substrate having a first conductivity type; source/drain regions of a second conductivity type; lightly doped regions covering the bottom of the source/drain regions and surrounding the source/drain regions, the lightly doped regions having the second conductivity type and a lower impurity concentration than an impurity concentration of the source/drain regions; an off-set region surrounding the lightly doped regions, the off-set region having the first conductivity type, the off-set region having a lower impurity concentration than the impurity concentration of the lightly doped regions; and a channel stopper region having the first conductivity type, the channel stopper region having a higher impurity concentration than the impurity concentration of the off-set region, the channel stopper region surrounding the off-set region, the channel stopper region having projected portions under a gate electrode, the projected por

Abstract: It is the object of the invention to provide a semiconductor device with a high-voltage breakdown characteristic against an overvoltage surge from an inductance load. The semiconductor device according to the invention has a lower withstand voltage of a substrate diode compared with that between source and drain electrodes, and a P.sup.- -substrate has an increased impurity concentration. The inverse surge generated by the inductance load is absorbed by the substrate diode and does not flow into a P-base of MOSFET. Accordingly, a parasitic NPN transistor does not turn on, and thereby the semiconductor device with the high withstand voltage against the inverse surge voltage can be provided.

Abstract: In a vertical power field effect transistor, a side surface of a gate electrode is covered with a side oxide film, and a groove is formed in self-alignment with the side oxide film to extend from a surface area of a silicon substrate between a pair of adjacent gate electrodes, to reach a base region. A tungsten film is filled into the groove thus formed, and a source electrode-is formed in contact with the tungsten film within the groove.

Abstract: A vertical field effect transistor of the structure having a gate pad and a gate finger, includes a semiconductor substrate of a first conduction type, and a first diffusion region of a second conduction type opposite to the first conduction type, formed in a principal surface of the substrate under the gate pad and the gate finger. A second diffusion region of the second conduction type is formed in the principal surface of the substrate and electrically connected to a source electrode so as to form a protection diode between the substrate and the second diffusion region. The second diffusion region is separated from the first diffusion region.