Patents by Inventor Mitsue Takahashi
Mitsue Takahashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11335783Abstract: A FeFET and a method of its manufacture are provided, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm<dr<150 nm, without impairing the data retention property of not less than 105 seconds and the data rewrite endurance property of not less than 108 times, of those that have hitherto been developed, and the FeFET allowing a memory window of 0.40 V or more when a sweep amplitude of the gate voltage is not more than 3.3 V.Type: GrantFiled: May 8, 2020Date of Patent: May 17, 2022Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, WACOM R&D CORPORATIONInventors: Shigeki Sakai, Mitsue Takahashi, Masaki Kusuhara, Masayuki Toda, Masaru Umeda, Yoshikazu Sasaki
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Patent number: 11069713Abstract: A semiconductor memory element is provided including a laminated structure, in which a memory member and a conductor are superposed on a semiconductor substrate. The memory member has a bottom surface in contact with the semiconductor substrate, an upper surface in contact with the conductor, and side surfaces, which are in contact with and surrounded by a partition wall; the bottom surface of the memory member has a width of equal to or not more than 100 nm; a shortest distance between the conductor and the semiconductor substrate is twice or more of the width of the bottom surface of the memory member; the side surface of the memory member has a width, which is either the same as the width of the bottom surface and constant at any position above the bottom surface, or the widest at a position other than the bottom surface and above the bottom surface.Type: GrantFiled: July 3, 2017Date of Patent: July 20, 2021Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, WACOMInventors: Mitsue Takahashi, Shigeki Sakai, Masaki Kusuhara, Masayuki Toda, Masaru Umeda, Yoshikazu Sasaki
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Publication number: 20200279927Abstract: [Object] To provide a FeFET and a method of its manufacture, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm<dr<150, without impairing the data retention property of not less than 105 seconds and the data rewrite withstand property of not less than 108 times, of those that have hitherto been developed, and the FeFET allowing data to be written with a writing voltage whose absolute value is not more than 3.3 volts. [Means for Solving] In methods of making a device in which an insulator, a film made of constituent elements of a bismuth layered perovskite crystalline ferroelectric and a metal are sequentially formed in the indicated order on a semiconductor substrate and thereafter are annealed for ferroelectric crystallization, thereby preparing the device composed of the semiconductor, insulator, ferroelectric and metal, a method of making a semiconductor ferroelectric memory element in which the film is composed of Ca.Type: ApplicationFiled: May 8, 2020Publication date: September 3, 2020Inventors: Shigeki SAKAI, Mitsue TAKAHASHI, Masaki KUSUHARA, Masayuki TODA, Masaru UMEDA, Yoshikazu SASAKI
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Patent number: 10686043Abstract: [Object] To provide a FeFET and a method of its manufacture, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm<dr<150, without impairing the data retention property of not less than 105 seconds and the data rewrite withstand property of not less than 108 times, of those that have hitherto been developed, and the FeFET allowing data to be written with a writing voltage whose absolute value is not more than 3.3 volts. [Means for Solving] In methods of making a device in which an insulator, a film made of constituent elements of a bismuth layered perovskite crystalline ferroelectric and a metal are sequentially formed in the indicated order on a semiconductor substrate and thereafter are annealed for ferroelectric crystallization, thereby preparing the device composed of the semiconductor, insulator, ferroelectric and metal, a method of making a semiconductor ferroelectric memory element in which the film is composed of Ca.Type: GrantFiled: April 21, 2017Date of Patent: June 16, 2020Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, WACOM R&D CORPORATIONInventors: Shigeki Sakai, Mitsue Takahashi, Masaki Kusuhara, Masayuki Toda, Masaru Umeda, Yoshikazu Sasaki
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Publication number: 20190273086Abstract: A semiconductor memory element is provided including a laminated structure, in which a memory member and a conductor are superposed on a semiconductor substrate. The memory member has a bottom surface in contact with the semiconductor substrate, an upper surface in contact with the conductor, and side surfaces, which are in contact with and surrounded by a partition wall; the bottom surface of the memory member has a width of equal to or not more than 100 nm; a shortest distance between the conductor and the semiconductor substrate is twice or more of the width of the bottom surface of the memory member; the side surface of the memory member has a width, which is either the same as the width of the bottom surface and constant at any position above the bottom surface, or the widest at a position other than the bottom surface and above the bottom surface.Type: ApplicationFiled: July 3, 2017Publication date: September 5, 2019Applicants: National Institute of Advanced Industrial Science and Technology, WACOM R&D CorporationInventors: Mitsue TAKAHASHI, Shigeki SAKAI, Masaki KUSUHARA, Masayuki TODA, Masaru UMEDA, Yoshikazu SASAKI
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Patent number: 10192972Abstract: Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body (11) and a gate electrode conductor (4) are sequentially laminated in this order on a semiconductor base (10) that has a source region (12) and a drain region (13). The insulating body (11) is configured by laminating a first insulating body (1) and a second insulating body (2) in this order on the base (10), and the second insulating body (2) is mainly composed of an oxide of strontium, calcium, bismuth and tantalum.Type: GrantFiled: August 29, 2017Date of Patent: January 29, 2019Assignee: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Shigeki Sakai, Wei Zhang, Mitsue Takahashi
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Publication number: 20180130909Abstract: A ferroelectric device and a manufacturing method are provided. While holding a nonvolatile memory retention capability and a multiple rewriting endurance as the distinctive features of a ferroelectric device, the disclosed ferroelectric device is wider in memory window and more adaptively made microfiner than a conventional ferroelectric device that has used a ferroelectric mainly constituted of Sr—Bi—Ta—O as an oxide of strontium, bismuth and tantalum. Directly on or with intermediary of an insulator on a semiconductor there are layered a first ferroelectric and a conductor to form a gate stack, the first ferroelectric being mainly constituted of Sr—Ca—Bi—Ta—O as an oxide of strontium, calcium, bismuth and tantalum and being built up by a metal organic vapor deposition technique from a suitable film-forming raw material. The gate stack is heat-treated to cause the first ferroelectric to develop its ferroelectricity.Type: ApplicationFiled: August 11, 2017Publication date: May 10, 2018Inventors: Shigeki SAKAI, Mitsue TAKAHASHI, Masaki KUSUHARA, Masayuki TODA, Masaru UMEDA
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Publication number: 20180006130Abstract: Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body (11) and a gate electrode conductor (4) are sequentially laminated in this order on a semiconductor base (10) that has a source region (12) and a drain region (13). The insulating body (11) is configured by laminating a first insulating body (1) and a second insulating body (2) in this order on the base (10), and the second insulating body (2) is mainly composed of an oxide of strontium, calcium, bismuth and tantalum.Type: ApplicationFiled: August 29, 2017Publication date: January 4, 2018Inventors: Shigeki SAKAI, Wei ZHANG, Mitsue TAKAHASHI
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Patent number: 9818869Abstract: A ferroelectric device and a manufacturing method are provided. While holding a nonvolatile memory retention capability and a multiple rewriting endurance as the distinctive features of a ferroelectric device, the disclosed ferroelectric device is wider in memory window and more adaptively made microfiner than a conventional ferroelectric device that has used a ferroelectric mainly constituted of Sr—Bi—Ta—O as an oxide of strontium, bismuth and tantalum. Directly on or with intermediary of an insulator on a semiconductor there are layered a first ferroelectric and a conductor to form a gate stack, the first ferroelectric being mainly constituted of Sr—Ca—Bi—Ta—O as an oxide of strontium, calcium, bismuth and tantalum and being built up by a metal organic vapor deposition technique from a suitable film-forming raw material. The gate stack is heat-treated to cause the first ferroelectric to develop its ferroelectricity.Type: GrantFiled: July 24, 2014Date of Patent: November 14, 2017Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, WACOM R&D CORPORATIONInventors: Shigeki Sakai, Mitsue Takahashi, Masaki Kusuhara, Masayuki Toda, Masaru Umeda
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Publication number: 20170309488Abstract: [Object] To provide a FeFET and a method of its manufacture, the FeFET having a ferroelectric whose film thickness (dr) is made small and so nanofine as to range in: 59 nm<dr<150, without impairing the data retention property of not less than 105 seconds and the data rewrite withstand property of not less than 108 times, of those that have hitherto been developed, and the FeFET allowing data to be written with a writing voltage whose absolute value is not more than 3.3 volts. [Means for Solving] In methods of making a device in which an insulator, a film made of constituent elements of a bismuth layered perovskite crystalline ferroelectric and a metal are sequentially formed in the indicated order on a semiconductor substrate and thereafter are annealed for ferroelectric crystallization, thereby preparing the device composed of the semiconductor, insulator, ferroelectric and metal, a method of making a semiconductor ferroelectric memory element in which the film is composed of Ca.Type: ApplicationFiled: April 21, 2017Publication date: October 26, 2017Inventors: Shigeki SAKAI, Mitsue TAKAHASHI, Masaki KUSUHARA, Masayuki TODA, Masaru UMEDA, Yoshikazu SASAKI
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Patent number: 9780186Abstract: Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body (11) and a gate electrode conductor (4) are sequentially laminated in this order on a semiconductor base (10) that has a source region (12) and a drain region (13). The insulating body (11) is configured by laminating a first insulating body (1) and a second insulating body (2) in this order on the base (10), and the second insulating body (2) is mainly composed of an oxide of strontium, calcium, bismuth and tantalum.Type: GrantFiled: May 30, 2013Date of Patent: October 3, 2017Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Shigeki Sakai, Wei Zhang, Mitsue Takahashi
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Publication number: 20160247932Abstract: A ferroelectric device and a manufacturing method are provided. While holding a nonvolatile memory retention capability and a multiple rewriting endurance as the distinctive features of a ferroelectric device, the disclosed ferroelectric device is wider in memory window and more adaptively made microfiner than a conventional ferroelectric device that has used a ferroelectric mainly constituted of Sr—Bi—Ta—O as an oxide of strontium, bismuth and tantalum. Directly on or with intermediary of an insulator on a semiconductor there are layered a first ferroelectric and a conductor to form a gate stack, the first ferroelectric being mainly constituted of Sr—Ca—Bi—Ta—O as an oxide of strontium, calcium, bismuth and tantalum and being built up by a metal organic vapor deposition technique from a suitable film-forming raw material. The gate stack is heat-treated to cause the first ferroelectric to develop its ferroelectricity.Type: ApplicationFiled: July 24, 2014Publication date: August 25, 2016Inventors: Shigeki SAKAI, Mitsue TAKAHASHI, Masaki KUSUHARA, Masayuki TODA, Masaru UMEDA
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Publication number: 20150171183Abstract: Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body (11) and a gate electrode conductor (4) are sequentially laminated in this order on a semiconductor base (10) that has a source region (12) and a drain region (13). The insulating body (11) is configured by laminating a first insulating body (1) and a second insulating body (2) in this order on the base (10), and the second insulating body (2) is mainly composed of an oxide of strontium, calcium, bismuth and tantalum.Type: ApplicationFiled: May 30, 2013Publication date: June 18, 2015Inventors: Shigeki Sakai, Wei Zhang, Mitsue Takahashi
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Patent number: 8159873Abstract: There is provided a semiconductor integrated circuit including a state detection enhancement circuit which includes an input terminal and an output terminal and has a function of generating an electric potential of a magnitude capable of performing nonvolatile memory writing into a nonvolatile memory circuit based on an electric potential input to the input terminal and outputting the electric potential of the magnitude to the output terminal, and the nonvolatile memory circuit has a nonvolatile memory function and an input terminal of the nonvolatile memory circuit is connected to the output of the state detection enhancement circuit.Type: GrantFiled: October 29, 2007Date of Patent: April 17, 2012Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Mitsue Takahashi, Shigeki Sakai
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Patent number: 8139388Abstract: This invention has the purpose of providing a nonvolatile semiconductor storage device which is capable of entering multivalued storage in a FeFET unit without requiring preparation of a plurality of voltage sources. The nonvolatile semiconductor storage device is provided with multivalued ferroelectric memory cells which impart varied quantities of polarization to a ferroelectric material by applying pulse voltages having one and the same height and varied widths and consequently produce varied states of storage in conformity with the varied quantities of polarization.Type: GrantFiled: September 23, 2009Date of Patent: March 20, 2012Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Mitsue Takahashi, Shigeki Sakai, Shouyu Wang, Ken Takeuchi
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Patent number: 8081499Abstract: A field-effect transistor for nonvolatile memory holding use and a field-effect transistor for logical operation use are manufactured in the same structure on the same semiconductor substrate without separately providing manufacturing processes for the field-effect transistors for the two uses. Both a memory circuit and a logic circuit of a semiconductor integrated circuit are composed of n-channel and p-channel field-effect transistors including a memory holding material in a gate insulating structure. A logical operation state, a memory writing state and a nonvolatile memory holding state are electrically switched by controlling the level and application timing of a voltage to be applied between a gate conductor and a substrate region of the n-channel and p-channel field-effect transistors including the memory holding material in the gate insulating structure.Type: GrantFiled: April 13, 2006Date of Patent: December 20, 2011Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Mitsue Takahashi, Shigeki Sakai
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Publication number: 20110038201Abstract: There is provided a semiconductor integrated circuit including a state detection enhancement circuit which includes an input terminal and an output terminal and has a function of generating an electric potential of a magnitude capable of performing nonvolatile memory writing into a nonvolatile memory circuit based on an electric potential input to the input terminal and outputting the electric potential of the magnitude to the output terminal, and the nonvolatile memory circuit has a nonvolatile memory function and an input terminal of the nonvolatile memory circuit is connected to the output of the state detection enhancement circuit.Type: ApplicationFiled: October 29, 2007Publication date: February 17, 2011Applicant: NATIONAL INSTITUTE OF ADVANCED IND.SCI AND TECHInventors: Mitsue Takahashi, Shigeki Sakai
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Publication number: 20100073988Abstract: This invention has the purpose of providing a nonvolatile semiconductor storage device which is capable of entering multivalued storage in a FeFET unit without requiring preparation of a plurality of voltage sources. The nonvolatile semiconductor storage device is provided with multivalued ferroelectric memory cells which impart varied quantities of polarization to a ferroelectric material by applying pulse voltages having one and the same height and varied widths and consequently produce varied states of storage in conformity with the varied quantities of polarization.Type: ApplicationFiled: September 23, 2009Publication date: March 25, 2010Applicant: Nat Inst of Adv Industrial Sci and TechInventors: Mitsue TAKAHASHI, Shigeki Sakai, Shouyu Wang, Ken Takeuchi
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Publication number: 20090059646Abstract: A field-effect transistor for nonvolatile memory holding use and a field-effect transistor for logical operation use are manufactured in the same structure on the same semiconductor substrate without separately providing manufacturing processes for the field-effect transistors for the two uses. Both a memory circuit and a logic circuit of a semiconductor integrated circuit are composed of n-channel and p-channel field-effect transistors including a memory holding material in a gate insulating structure. A logical operation state, a memory writing state and a nonvolatile memory holding state are electrically switched by controlling the level and application timing of a voltage to be applied between a gate conductor and a substrate region of the n-channel and p-channel field-effect transistors including the memory holding material in the gate insulating structure.Type: ApplicationFiled: April 13, 2006Publication date: March 5, 2009Applicant: NATIONAL INSTITUTE OF ADVANCED IND. SCI & TECHInventors: Mitsue Takahashi, Shigeki Sakai
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Patent number: 6445633Abstract: A read amplifier circuit includes an equalize start circuit. Based on a preamp enable signal PAE and an equalize signal IOEQ, the equalize start circuit generates an equalize start signal EQ for starting equalization at the timing when the preamp enable signal PAE is activated. Simultaneously with activation of a preamplifier by the preamp enable signal PAE, a pair of read lines GIOR and /GIOR is cut off from the preamplifier, and a P channel MOS transistor starts equalization of the pair of read lines GIOR and /GIOR. In this way, it is possible to start equalization of the paired read lines at the same time that the output signal is supplied to the preamplifier.Type: GrantFiled: February 26, 2001Date of Patent: September 3, 2002Assignees: Mitsubishi Kabushiki Kaisha, Mitsubishi Electric Engineering Company LimitedInventors: Mitsue Takahashi, Hiroaki Tanizaki