Patents by Inventor Mitsufumi Naoe
Mitsufumi Naoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9508559Abstract: A semiconductor wafer including patterns transferred to a plurality of shot regions of the semiconductor wafer respectively, a plurality of chip regions being formed in the plurality of shot regions respectively, a plurality of first dummy patterns being formed respectively in a first chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of first dummy patterns being arranged repeatedly in a first manner, a plurality of second dummy patterns being formed respectively in a second chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of second dummy patterns being arranged repeatedly in a second manner different from the first manner.Type: GrantFiled: September 18, 2013Date of Patent: November 29, 2016Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shoko Saito, Tomoyuki Okada, Kanji Takeuchi, Mitsufumi Naoe, Masahiko Minemura, Yukihiro Sato, Yoshito Konno, Yasuhiko Inada, Tomoaki Inaoka, Naoya Sashida
-
Patent number: 8778779Abstract: A method for producing semiconductor device includes: performing first, second and third exposures of a photoresist film formed on a semiconductor wafer via a mask; wherein: first, second and third shot regions respectively defined by the first, second and third exposures are aligned in a first direction; the mask has a shot region including a peripheral scribe region having a first and second side crossing the first direction; the photoresist film is of positive type, a first pattern is formed as a light shielding pattern disposed on the first side, and a second pattern is formed as a light transmitting region disposed on the second side; the first and second exposures are performed in such a manner that the first and second patterns do not overlap each other; and the second and third exposures are performed in such a manner that the first and second patterns overlap each other.Type: GrantFiled: August 10, 2012Date of Patent: July 15, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Mitsufumi Naoe
-
Publication number: 20140110712Abstract: A semiconductor wafer including patterns transferred to a plurality of shot regions of the semiconductor wafer respectively, a plurality of chip regions being formed in the plurality of shot regions respectively, a plurality of first dummy patterns being formed respectively in a first chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of first dummy patterns being arranged repeatedly in a first manner, a plurality of second dummy patterns being formed respectively in a second chip region of the plurality of chip regions of each of the plurality of shot regions, the plurality of second dummy patterns being arranged repeatedly in a second manner different from the first manner.Type: ApplicationFiled: September 18, 2013Publication date: April 24, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shoko Saito, Tomoyuki Okada, Kanji Takeuchi, MITSUFUMI NAOE, Masahiko Minemura, Yukihiro Sato, Yoshito Konno, Yasuhiko Inada, Tomoaki Inaoka, Naoya SASHIDA
-
Publication number: 20130082408Abstract: A method for producing semiconductor device includes: performing first, second and third exposures of a photoresist film formed on a semiconductor wafer via a mask; wherein: first, second and third shot regions respectively defined by the first, second and third exposures are aligned in a first direction; the mask has a shot region including a peripheral scribe region having a first and second side crossing the first direction; the photoresist film is of positive type, a first pattern is formed as a light shielding pattern disposed on the first side, and a second pattern is formed as a light transmitting region disposed on the second side; the first and second exposures are performed in such a manner that the first and second patterns do not overlap each other; and the second and third exposures are performed in such a manner that the first and second patterns overlap each other.Type: ApplicationFiled: August 10, 2012Publication date: April 4, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: MITSUFUMI NAOE
-
Patent number: 8280147Abstract: A pattern verification apparatus includes a correction section creating a plurality of first data pieces; a determination section performing light intensity simulation to create a plurality of plots, determine whether or not each of the plurality of simulation result plots falls within an allowable range, and recognize two or more simulation result plots which do not fall within the allowable range as a plurality of second data pieces; an extraction section extracting a reference pattern of the plurality of original design patterns corresponding to the plurality of second data pieces; and a classifying section classifying the plurality of second data pieces into categories of the reference pattern.Type: GrantFiled: February 5, 2010Date of Patent: October 2, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Mitsufumi Naoe, Toru Miyauchi, Tomoyuki Okada, Seiji Makino, Koichi Suzuki, Masakazu Ohseki
-
Patent number: 8223403Abstract: An inspection apparatus of a mask for exposure that has a light shielding region 3 and a half-tone region 2 on a transparent substrate 1, includes a storage unit stored with half-tone pattern area data specifying an existing area of the half-tone region 2, a pattern detection unit 22 acquiring a binary image of an area in which to scan over the surface of the transparent substrate by a relative movement with respect to the transparent substrate, and a control unit 20 making effective a detecting operation of the pattern detection unit in the area on the transparent substrate that is specified by the half-tone pattern area data, and making ineffective the detecting operation of the pattern detection unit outside the specified area.Type: GrantFiled: December 5, 2006Date of Patent: July 17, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Tsutomu Horie, Mitsufumi Naoe
-
Patent number: 7855035Abstract: According to the present invention, provided is a method of manufacturing a electronic device including forming a film over a substrate, performing a photoresist over the film, performing a first exposure by using an exposure mask which includes a scribe region and a inspection mark formed in a first side of the scribe region, and performing a second exposure so that a region that is exposed to the first side in the first exposure is exposed to a second side of the scribe region which is opposite to the first side, wherein, in the second exposure, an exposure light is incident on a region where the inspection mark is projected in the first exposure.Type: GrantFiled: October 18, 2007Date of Patent: December 21, 2010Assignee: Fujitsu Semiconductor LimitedInventor: Mitsufumi Naoe
-
Publication number: 20100232679Abstract: A pattern verification apparatus includes a correction section creating a plurality of first data pieces; a determination section performing light intensity simulation to create a plurality of plots, determine whether or not each of the plurality of simulation result plots falls within an allowable range, and recognize two or more simulation result plots which do not fall within the allowable range as a plurality of second data pieces; an extraction section extracting a reference pattern of the plurality of original design patterns corresponding to the plurality of second data pieces; and a classifying section classifying the plurality of second data pieces into categories of the reference pattern.Type: ApplicationFiled: February 5, 2010Publication date: September 16, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Mitsufumi Naoe, Toru Miyauchi, Tomoyuki Okada, Seiji Makino, Koichi Suzuki, Masakazu Ohseki
-
Publication number: 20080096113Abstract: According to the present invention, provided is a method of manufacturing a electronic device including forming a film over a substrate, performing a photoresist over the film, performing a first exposure by using an exposure mask which includes a scribe region and a inspection mark formed in a first side of the scribe region, and performing a second exposure so that a region that is exposed to the first side in the first exposure is exposed to a second side of the scribe region which is opposite to the first side, wherein, in the second exposure, an exposure light is incident on a region where the inspection mark is projected in the first exposure.Type: ApplicationFiled: October 18, 2007Publication date: April 24, 2008Applicant: FUJITSU LIMITEDInventor: Mitsufumi Naoe
-
Publication number: 20070285728Abstract: An inspection apparatus of a mask for exposure that has a light shielding region 3 and a half-tone region 2 on a transparent substrate 1, includes a storage unit stored with half-tone pattern area data specifying an existing area of the half-tone region 2, a pattern detection unit 22 acquiring a binary image of an area in which to scan over the surface of the transparent substrate by a relative movement with respect to the transparent substrate, and a control unit 20 making effective a detecting operation of the pattern detection unit in the area on the transparent substrate that is specified by the half-tone pattern area data, and making ineffective the detecting operation of the pattern detection unit outside the specified area.Type: ApplicationFiled: December 5, 2006Publication date: December 13, 2007Applicant: FUJITSU LIMITEDInventors: Tsutomu Horie, Mitsufumi Naoe
-
Patent number: 6372392Abstract: A transparent optical device is provided with a transparent medium having a front side, at least a portion of the front side being adapted for receiving light. A porous layer is formed on substantially all areas of the front side which are adapted for receiving light. The transparent optical device may have a recessed surface area which is recessed below a remainder area of the front side to define a phase shift photomask. The transparent medium may be made of synthesized silica. The porous layer may be formed by reactive ion etching using gaseous plasma of halogenized hydrocarbon. The front side of the transparent medium may have a portion not adapted for receiving light which may have a metal pattern formed thereon. In producing the transparent optical mask, the porous layer may be formed before or after the metal pattern. The transparent optical device may be formed in an etching chamber in which etching depth is monitored by measuring the transmissivity of a preselected portion of the transparent medium.Type: GrantFiled: November 6, 1997Date of Patent: April 16, 2002Assignee: Fujitsu LimitedInventors: Eiichi Hoshino, Masanori Onodera, Naoyuki Ishiwata, Kazumasa Doi, Mitsufumi Naoe