Abstract: A packet switching system for achieving high-speed packet switching on data lines having the X.25 protocol of the C.C.I.T.T. It includes a plurality of data line apparatuses (DLC: 10, 11, and 1N), a call connection control information transfer bus commonly connected to the plurality of data line apparatuses (CB: 2), a specialized data transfer bus for data packets (DB: 4), a packet buffer state information transfer bus for transmitting and receiving call state information (SB: 6), and a call connection controlling processor connected to the call connection control information transfer bus (CP: 3). Each of the data line apparatuses has a receive packet storing circuit (DTRQ: 102) provided with a receive packet buffer of the first-in random out (FIRO) memory, and a transmit packet storing circuit (DTSQ: 105) provided with a transmit packet buffer of the FIRO memory.