Abstract: A semiconductor integrated circuit device comprising a first circuit forming a random logic and outputting a plurality of first parallel data of plural bits, a second circuit which receives the plurality of first parallel data and supplies a plurality of second parallel data of plural bits to the first circuit, and a test circuit which divides a part of external parallel data of plural bits smaller in number than the first parallel data into a plurality of third parallel data of plural bits in such a manner that the plurality of third parallel data correspond in number to the plurality of first parallel data.

Abstract: A gate array comprises a semiconductor substrate, a plurality of mutually parallel basic cell columns each made up of a plurality of basic cells formed on the semiconductor substrate, where each of the basic cells comprise a pair of first p-channel transistor and first n-channel transistor, a plurality of interconnection regions each formed between two mutually adjacent ones of the basic cell columns, and specific cells buried in one or a plurality of predetermined ones of the interconnection regions, where each of the specific cells comprise at least a second p-channel transistor and a second n-channel transistor which constitute a transmission gate.

Abstract: In a semiconductor device comprising a memory cell array and a test pattern generating circuit, the test pattern generating circuit generates the test pattern and transmits the test pattern to the memory cell array when receiving the least significant bit signal of address signals supplied to the memory cell array and the control signal.