Abstract: A power conversion apparatus includes: matrix converter circuitry to perform power conversion between a primary side electric power and a secondary side electric power; rectifier circuitry to convert the primary side electric power to charge a capacitor; and control circuitry to: set a changeover reference voltage at a first reference voltage when the primary side voltage magnitude is a first voltage magnitude and set the changeover reference voltage at a second reference voltage when the primary side voltage magnitude is a second voltage magnitude; and select, based on the changeover reference voltage and the terminal voltage, a connection state from: a first connection state in which the rectifier circuitry is connected to the capacitor by a first route including a current limit device; and a second connection state in which the rectifier circuitry is connected to the capacitor by a second route that bypasses the current limit device.

Abstract: A power conversion apparatus includes: matrix converter circuitry to perform power conversion between a primary side electric power and a secondary side electric power; rectifier circuitry to convert the primary side electric power to charge a capacitor; and control circuitry to: set a changeover reference voltage at a first reference voltage when the primary side voltage magnitude is a first voltage magnitude and set the changeover reference voltage at a second reference voltage when the primary side voltage magnitude is a second voltage magnitude; and select, based on the changeover reference voltage and the terminal voltage, a connection state from: a first connection state in which the rectifier circuitry is connected to the capacitor by a first route including a current limit device; and a second connection state in which the rectifier circuitry is connected to the capacitor by a second route that bypasses the current limit device.

Abstract: A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electrode is a nMOS gate electrode formed in an nMOS region of the transistor configuration, wherein the polycrystalline silicon grains included in the bottom layer of the first gate electrode have a greater particle diameter than the polycrystalline grains included in the upper layer of the second gate electrode.

Abstract: A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electrode is a nMOS gate electrode formed in an nMOS region of the transistor configuration, wherein the polycrystalline silicon grains included in the bottom layer of the first gate electrode have a greater particle diameter than the polycrystalline grains included in the upper layer of the second gate electrode.

Abstract: A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electrode is a nMOS gate electrode formed in an nMOS region of the transistor configuration, wherein the polycrystalline silicon grains included in the bottom layer of the first gate electrode have a greater particle diameter than the polycrystalline grains included in the upper layer of the second gate electrode.

Abstract: A method of manufacturing a semiconductor device includes forming a gate insulating film over a semiconductor substrate, forming a silicon film over the gate insulating film, forming a resist pattern over the silicon film, etching the silicon film to form a protrusion portion of the silicon film, forming a dummy film over the silicon film, etching the dummy film so that the dummy film is partially remained on sidewalls of the protrusion portion, etching the silicon film using the remaining dummy film to form a gate electrode, and performing ion implantation into the semiconductor substrate to form source/drain regions.

Abstract: A method of manufacturing a semiconductor device has forming a first silicon film over the first insulating film, forming a second silicon film over the first silicon film, a first etching the second silicon film in a depth, which the first silicon film is not exposed, in first condition, a second etching a remaining portion of the second silicon film and the first silicon film in a depth, which the first insulating film is not exposed, in second condition which gives a higher vertical etching component ratio than the first condition; and a third etching a remaining portion of the first silicon film in third condition which an etching rate for the first silicon film is larger than an etching rate for the first insulating film as compared to the second condition, wherein an impurity concentration of a first conductivity type of the first silicon film is higher than an impurity concentration of first conductivity type of the second silicon film.

Abstract: A method of manufacturing a semiconductor device includes forming a gate insulating film over a semiconductor substrate, forming a silicon film over the gate insulating film, forming a resist pattern over the silicon film, etching the silicon film to form a protrusion portion of the silicon film, forming a dummy film over the silicon film, etching the dummy film so that the dummy film is partially remained on sidewalls of the protrusion portion, etching the silicon film using the remaining dummy film to form a gate electrode, and performing ion implantation into the semiconductor substrate to form source/drain regions.

Abstract: A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at least a bottom layer and an upper layer including polycrystalline silicon grains, wherein the first gate electrode is a nMOS gate electrode formed in an nMOS region of the transistor configuration, wherein the polycrystalline silicon grains included in the bottom layer of the first gate electrode have a greater particle diameter than the polycrystalline grains included in the upper layer of the second gate electrode.

Abstract: A method of manufacturing a semiconductor device has forming a first silicon film over the first insulating film, forming a second silicon film over the first silicon film, a first etching the second silicon film in a depth, which the first silicon film is not exposed, in first condition, a second etching a remaining portion of the second silicon film and the first silicon film in a depth, which the first insulating film is not exposed, in second condition which gives a higher vertical etching component ratio than the first condition; and a third etching a remaining portion of the first silicon film in third condition which an etching rate for the first silicon film is larger than an etching rate for the first insulating film as compared to the second condition, wherein an impurity concentration of a first conductivity type of the first silicon film is higher than an impurity concentration of first conductivity type of the second silicon film.

Abstract: A semiconductor device manufacture method includes the steps of forming a resist layer above a work target layer; exposing and developing the resist layer to form resist patterns including isolated pattern and dense patterns; monitoring widths of isolated and dense pattern of the resist patterns to determine trimming amounts of linewidths to be reduced; determining etching conditions for realizing the trimming amounts of both the isolated and dense patterns, the etching conditions using mixed gas of a gas having a function of mainly enhancing etching and a gas having a function of mainly suppressing etching; trimming the resist pattern under said determined etching conditions; and etching the work target layer by using said trimmed resist patterns. A desired pattern width an be realized stably by trimming using plasma etching.

Abstract: A method for manufacturing a semiconductor device includes: forming a first photoresist pattern on a second hard mask by use of ArF; forming first and second openings in the second hard mask by use of the first photoresist pattern as an etching mask; forming third and fourth openings in a first hard mask under the first and second openings; forming a partial trench (first trench) and a trench for a full trench (second trench) in an SOI substrate (semiconductor substrate) under the first and second openings; and forming the trench for a full trench into a full trench by etching the trench for a full trench through the fourth opening exposed through a third window of a second photoresist pattern.

Abstract: A method for manufacturing a semiconductor device includes: forming a first photoresist pattern on a second hard mask by use of ArF; forming first and second openings in the second hard mask by use of the first photoresist pattern as an etching mask; forming third and fourth openings in a first hard mask under the first and second openings; forming a partial trench (first trench) and a trench for a full trench (second trench) in an SOI substrate (semiconductor substrate) under the first and second openings; and forming the trench for a full trench into a full trench by etching the trench for a full trench through the fourth opening exposed through a third window of a second photoresist pattern.

Abstract: A semiconductor device manufacture method includes the steps of forming a resist layer above a work target layer; exposing and developing the resist layer to form resist patterns including isolated pattern and dense patterns; monitoring widths of isolated and dense pattern of the resist patterns to determine trimming amounts of linewidths to be reduced; determining etching conditions for realizing the trimming amounts of both the isolated and dense patterns, the etching conditions using mixed gas of a gas having a function of mainly enhancing etching and a gas having a function of mainly suppressing etching; trimming the resist pattern under said determined etching conditions; and etching the work target layer by using said trimmed resist patterns. A desired pattern width an be realized stably by trimming using plasma etching.