Abstract: Address bits AU1 to AU4 designating rows of a memory 1 at random are successively given thereto. Respective Q lines of each row of the memory 1 are connected in series to register groups SR-R1 to SR-R4. An address bit of a row designated with AU1 to AU4 is stored in each register group. Respective data of the register groups SR-R1 to SR-R4 is supplied to output ports SO1 to SO4 in series by selectors SL1 to SL4. Instead of the register groups SR-R1 to SR-R4 and the selectors SL1 to SL14, shift registers can be used.

Abstract: Input data of 8 rows and 8 columns are input from an input terminal (IN) in the sequential order of columns and supplied through a first rearranging circuit (41) of 64 words to a 4-degree first inner product calculating circuit (42). An output of this inner product calculating circuit (42) is supplied through a second rearranging circuit (43) of 64 words to an 8 degree second inner product calculating circuit (44). An output of the inner product calculating circuit (44) is supplied to a 4-degree third inner product calculating circuit (45), and an output of the inner product calculating circuit (45) is delivered through a rearranging circuit (46) to an output terminal (OUT). Therefore, the inner product calculating circuit can be reduced in circuit scale, the circuit arrangement can be simplified and the number of calculation can be reduced to thereby enable a high speed calculation to be carried out.

Abstract: A data processing circuit multiplies, by 2.sup.a, input data supplied in a time-division multiplexed manner over a plurality of lines. The data processing circuit includes first, second, and third data selectors each having first, second, and third input terminals and a single output terminal. The first input terminal of the first selector is supplied with an input signal of "0". A first input line is connected in common to the second input terminal of the first data selector and the first input terminal of the second data selector. A second input line is connected in common to the third input terminal of the first data selector and the second input terminal of the second data selector. A third input line is connected in common to the third input terminal of the second data selector and the second input terminal of the third data selector. The first, second, and third input lines are supplied input data in a time-division multiplexed manner.

Abstract: A motion vector detection device in which the absolute value of the difference between a plurality of sets of representative points, selected at the same interval as the search area consisting of Q.times.R pixels, and pixel data of the current field at the positions of the q.times.r pixel interval is calculated to find vectors, data of each vector are cumulatively summed to find the remainder, data of the remainder of each vector are compared to one another to find a motion vector and a motion vector is found at an interval less than q.times.r by interpolation from the motion vector and values of the remainder in its vicinity.

Abstract: An image information processing apparatus includes a detector for detecting the move vector of an image of the present relative to that of the preceding field; a circuit for processing, on the basis of the move vector, the image of the present field stored in a field memory; and a residual memory for storing the residual information calculated during the period in which the image data of one horizontal scanning line is inputted. The residual information stored in the residual memory is shunted into a blank area of the field memory during a predetermined interval after the period in which the image data is input. The processing circuit performs a wobble correction to correct any shaking of the image between fields or compresses the data quantity of the dynamic image in image transmission, and the information of one entire picture is processed after being divided into a plurality of blocks, whereby the storage capacity of the residual memory can be widely reduced.

Abstract: An image data processing apparatus selects and extracts the elements of a desired 8.times.8 matrix from four matrices in real space each having 8 rows and 8 columns and effects an inverse discrete cosine transform on the four matrices. The elements of the four matrices each of the 8 rows and 8 columns are arranged into four vectors each of 64 elements. The elements of the vectors are supplied serially to four 64-output serial-to-parallel converters, which output the elements in parallel. Data selectors then select the 64 elements of one of the vectors. Half of the selected elements are processed by a 32-element inner product processing circuit, which produces a first inner product output signal. The remaining selected elements are processed by another 32-element inner product processing circuit, which produces a second inner product output signal. The first and second inner product output signals are added into a final output signal by an adder.

Abstract: An inner product calculating circuit for executing a calculation of an inner product on the basis of one or more vector data and one or more coefficients. The circuit comprises a selective inverter for selectively inverting individual bits of the vector data; a bit position shifter for shifting, in accordance with the coefficients, the bit positions of the vector data inverted selectively by the selective inverter; a bit supplementer for supplementing, with either "1" or "0", any vacant bit of the vector data where the bit positions have been shifted by the bit position shifter; and an accumulator for accumulating the initial values preset in conformity with the coefficients and the vector data supplemented with "1" or "0" in any vacant bit thereof by the bit supplementer.

Abstract: An image data processing apparatus includes a <v> calculating block 7 for calculating a vector <v> from a vector <x> which has 64 elements in a real space and which has been generated as a sequence of image data in 8 rows and 8 columns in the real space, a <w> calculating block 8 for calculating a vector <w> from the vector <x> in the real space, and a <c> calculating block 9 for adding and subtracting elements of the vector <v> and elements of the vector <w>, thereby producing a vector <c> which has 64 elements in a space of spatial frequencies. The elements of the vector <c> in the space of spatial frequencies are arranged into data in 8 rows and 8 columns in the space of spatial frequencies.

Abstract: A serial-input-output multiplying circuit includes AND gates for providing partial products of an input number and a coefficient, a plurality of full adders supplied at input portions thereof with the partial products, unit delay elements for supplying carry outputs of the plurality of full adders to the input portions of the same full adders, and variable delay circuits for supplying sum outputs of the full adders to the input portions of following adders, wherein the product of the input number and the coefficient is serially obtained as a sum output of the full adder for the least significant digit.

Abstract: During a signal inputting period while a dynamic image signal of a present field is input, a movement vector detecting circuit 20 calculates a first movement vector V1 of a present field image with respect to a previous field image with a first accuracy. During a vertical blanking period after the signal inputting period, a second movement vector detecting circuit 30 calculates a second movement V2 according to the first movement vector V1 with a second accuracy higher than the first accuracy. A vector adder 34 composes the movement vectors V1 and V2 to obtain a final movement vector Vf. A second control circuit 71 outputs a reading address corresponding to the final movement vector Vf to a field memory 41, and the field memory 41 outputs an image signal corrected in camera shake. Accordingly, a camera shake correction accuracy is greatly improved without almost increasing a scale of a camera shake correcting circuit constructed as a one-chip circuit.

Abstract: A digital data processing circuit includes an adder circuit supplied with input data in a time-division multiplexed manner over a plurality of signal lines. The adder circuit is capable of executing additions at an optimum processing speed depending on the rate of the input data, and has a reduced circuit scale. The digital data processing circuit includes a 2-input data selector, a first register, a first full adder for supplying a carry output through the first register to one input terminal of the 2-input data selector, a second register, and a second full adder for supplying a carry output through the second register to the other input terminal of the 2-input data selector. The first and second full adders have input terminals for receiving first and second data supplied in a time-division multiplexed manner. The 2-input data selector is controlled to select the supplied carry outputs for producing the sum of the first and second data as sum outputs from the first and second full adders.