Abstract: A moving-picture processing apparatus has a pre-fetch memory pre-fetching a portion of a decoded picture stored in an external memory, and a miss/hit determination unit determining a manner in which a miss occurs in response to a read request to the pre-fetch memory.

Abstract: A dynamic reconfigurable circuit that implements optional processing by dynamically switching a processing content of a reconfigurable processing element (PE) and a connection content between the PEs in accordance with a context, includes: a configuration register section for setting a content of loop processing on the basis of the context, the loop processing content including an output source of an output signal from each of a set of the reconfigured PEs, an output destination of the output signal, and a condition for outputting the output signal to the output destination; and at least one counter circuit including a loop control section and an output register section that implement the set loop processing, that count the number of implementations of the loop processing implemented by the loop control section, and that output the output signal to the output destination based on the counted number of implementations and the condition.

Abstract: An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such a data buffer are provided for inputting data to the operation device, a data buffer control part is provided for controlling selection from these two paths and operation of the data buffer, and contents of path selection and operation control of the data buffer carried out by the data buffer control part are set according to the configuration information.

Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

Abstract: An optical network unit and an optical line terminal which efficiently control the data receiving and dechurning processes in a passive optical network. In a churning parameter memory subsystem, a first memory bank stores churning parameters that are currently used, while a second memory bank stores updates made to the churning parameters. Under the control of the churning parameter memory subsystem, those first and second memory banks change their roles with each other at a churning key updating time point. A data dechurning unit receives a data stream consisting of a plurality of frames and dechurns the information contained in the data stream, according to the stored churning parameters. When an update is done to the parameters in a certain frame, the data dechurning unit makes the update effective at the next frame, thus starting data dechurning operations from the next frame.

Abstract: A moving-picture processing apparatus has a pre-fetch memory pre-fetching a portion of a decoded picture stored in an external memory, and a miss/hit determination unit determining a manner in which a miss occurs in response to a read request to the pre-fetch memory.

Abstract: A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.

Abstract: A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.

Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

Abstract: A plurality of address creators are provided corresponding to a plurality of memories of ALU modules. The address creators create addresses for reading or writing data from the memories each time a connection configuration is switched. In creating addresses in the memories, the address creators enable operations to be set by using various types of parameters and set values by mounting special-purpose hardware for memory ports, so that addresses can be created at high-speed.

Abstract: A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.

Abstract: An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such a data buffer are provided for inputting data to the operation device, a data buffer control part is provided for controlling selection from these two paths and operation of the data buffer, and contents of path selection and operation control of the data buffer carried out by the data buffer control part are set according to the configuration information.

Abstract: A processor executes a predetermined operation process by switching a connection structure between a plurality of arithmetic and logic unit modules. Each of the arithmetic and logic unit modules includes a plurality of arithmetic and logic units. The arithmetic and logic unit modules include a first arithmetic and logic unit module that includes a plurality of arithmetic and logic units that executes various operation processes, and a second arithmetic and logic unit module that includes a plurality of arithmetic and logic units of which executable operation processes are limited compared with the first arithmetic and logic unit module.

Abstract: An optical network unit and an optical line terminal which efficiently control the data receiving and dechurning processes in a passive optical network. In a churning parameter memory subsystem, a first memory bank stores churning parameters that are currently used, while a second memory bank stores updates made to the churning parameters. Under the control of the churning parameter memory subsystem, those first and second memory banks change their roles with each other at a churning key updating time point. A data dechurning unit receives a data stream consisting of a plurality of frames and dechurns the information contained in the data stream, according to the stored churning parameters. When an update is done to the parameters in a certain frame, the data dechurning unit makes the update effective at the next frame, thus starting data dechurning operations from the next frame.

Abstract: An optical network unit and an optical line terminal which efficiently control the data receiving and dechurning processes in a passive optical network. In a churning parameter memory subsystem, a first memory bank stores churning parameters that are currently used, while a second memory bank stores updates made to the churning parameters. Under the control of the churning parameter memory subsystem, those first and second memory banks change their roles with each other at a churning key updating time point. A data dechurning unit receives a data stream consisting of a plurality of frames and dechurns the information contained in the data stream, according to the stored churning parameters. When an update is done to the parameters in a certain frame, the data dechurning unit makes the update effective at the next frame, thus starting data dechurning operations from the next frame.

Abstract: An address fault monitoring device and an ATM switching device capable of efficiently monitoring faults and quickly performing counter-fault process. Data storing unit stores data transmitted thereto. Write control unit controls the writing of data with respect to the data storing unit and notifies a read control side of write address information WD including information on a write address. Read control unit controls the reading of data with respect to the data storing unit and notifies the write control unit of read address information RD including information on a read address. Floating address measuring unit counts the number of floating addresses, and when a transmission error has occurred during transmission of the write address information WD or the read address information RD, it reckons the corresponding write or read address as a floating address.