Abstract: A semiconductor device includes: a first insulating layer; a semiconductor layer provided on the first insulating layer; a first semiconductor region selectively provided in the semiconductor layer; a second semiconductor region selectively provided in the semiconductor layer and spaced from the first semiconductor region; a first main electrode provided in contact with the first semiconductor region; a second main electrode provided in contact with the second semiconductor region; a second insulating layer provided on the semiconductor layer; a first conductive material provided in the second insulating layer above a portion of the semiconductor layer located between the first semiconductor region and the second semiconductor region; and a second conductive material provided in a trench provided in a portion of the semiconductor layer opposed to the first conductive material, being in contact with the first conductive material, and reaching the first insulating layer.

Abstract: According to one embodiment, the semiconductor device includes a drift region including a semiconductor of a first conductivity type; a first semiconductor region of a second conductivity type provided adjacently to the drift region; a main electrode, a plurality of first gate electrodes and a second gate electrode. The main electrode is provided adjacently to the first semiconductor region and electrically connected to the first semiconductor region, the first semiconductor region being disposed between the drift region and the main electrode. The first gate electrodes are provided along a boundary between the drift region and the first semiconductor region. The first gate electrode has a trench structure and faces the drift region and the first semiconductor region via a first gate insulating film. The second gate electrode of the trench structure is provided along the boundary between the drift region and the first semiconductor region.

Abstract: According to one embodiment, a semiconductor device is provided. The semiconductor device has a first region formed of semiconductor and a second region formed of semiconductor which borders the first region. An electrode is formed to be in ohmic-connection with the first region. A third region is formed to sandwich the first region. A first potential difference is produced between the first and the second regions in a thermal equilibrium state, according to a second potential difference between the third region and the first region.

Abstract: A semiconductor device includes: a semiconductor layer having a first end portion and a second end portion; a first main electrode provided on the first end portion and electrically connected to the semiconductor layer; a second main electrode provided on the second end portion and electrically connected to the semiconductor layer; a first gate electrode provided via a first gate insulating film in a plurality of first trenches formed from the first end portion toward the second end portion; and a second gate electrode provided via a second gate insulating film in a plurality of second trenches formed from the second end portion toward the first end portion. Spacing between a plurality of the first gate electrodes and spacing between a plurality of the second gate electrodes are 200 nm or less.

Abstract: The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer 4. A n-type drain layer 7 is formed in a position apart from the p-type base layer 4. On the surface of the region between the p-type base layer 4 and the n-type drain layer 7, a n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are alternately arranged from the p-type base layer 4 to the n-type drain layer 7. Further, in the region between the n-type source layer 5 and the n-type drain layer 7, a gate electrode 15 is formed via a gate insulating film 14.

Abstract: A transistor comprises: an insulating layer; a semiconductor layer provided on a major surface of the insulating layer; a gate insulating layer provided on the base region; and a gate electrode provided on the gate insulating layer. The semiconductor layer has a source portion having a plurality of source regions of a first conductivity type and a plurality of base contact regions of a second conductivity type, the source regions being alternated with the base contact regions, a drain portion of the first conductivity type, and a base region of the second conductivity type provided between the source portion and the drain portion, the base region being in contact with the source regions and the base contact regions. A junction between the source regions and the base region is closer to the drain portion side than a junction between the base contact regions and the base region.

Abstract: The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer 4. A n-type drain layer 7 is formed in a position apart from the p-type base layer 4. On the surface of the region between the p-type base layer 4 and the n-type drain layer 7, a n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are alternately arranged from the p-type base layer 4 to the n-type drain layer 7. Further, in the region between the n-type source layer 5 and the n-type drain layer 7, a gate electrode 15 is formed via a gate insulating film 14.

Abstract: A semiconductor device includes: a first insulating layer; a semiconductor layer provided on the first insulating layer; a first semiconductor region selectively provided in the semiconductor layer; a second semiconductor region selectively provided in the semiconductor layer and spaced from the first semiconductor region; a first main electrode provided in contact with the first semiconductor region; a second main electrode provided in contact with the second semiconductor region; a second insulating layer provided on the semiconductor layer; a first conductive material provided in the second insulating layer above a portion of the semiconductor layer located between the first semiconductor region and the second semiconductor region; and a second conductive material provided in a trench provided in a portion of the semiconductor layer opposed to the first conductive material, being in contact with the first conductive material, and reaching the first insulating layer.

Abstract: A MEMS (micro electro mechanical system) apparatus is equipped with a light-emitting circuit, having a light-emitting device, to emit light; a light-receiving circuit having a series circuit of series-connected light-receiving devices that receive the emitted light to generate a voltage; and a MEMS assembly driven by the generated voltage.

Abstract: The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer 4. A n-type drain layer 7 is formed in a position apart from the p-type base layer 4. On the surface of the region between the p-type base layer 4 and the n-type drain layer 7, a n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are alternately arranged from the p-type base layer 4 to the n-type drain layer 7. Further, in the region between the n-type source layer 5 and the n-type drain layer 7, a gate electrode 15 is formed via a gate insulating film 14.

Abstract: The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer. 4. A n-type drain layer 7 is formed in a position apart from the p-type base layer 4. On the surface of the region between the p-type base layer 4 and the n-type drain layer 7, a n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are alternately arranged from the p-type base layer 4 to the n-type drain layer 7. Further, in the region between the n-type source layer 5 and the n-type drain layer 7, a gate electrode 15 is formed via a gate insulating film 14.

Abstract: The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer 4. A n-type drain layer 7 is formed in a position apart from the p-type base layer 4. On the surface of the region between the p-type base layer 4 and the n-type drain layer 7, a n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are alternately arranged from the p-type base layer 4 to the n-type drain layer 7. Further, in the region between the n-type source layer 5 and the n-type drain layer 7, a gate electrode 15 is formed via a gate insulating film 14.

Abstract: A field-effect transistor includes a silicon layer formed on an insulating film, a first-conductivity-type base and a second-conductivity-type source layers formed in the silicon layer being adjacent to each other, a second-conductivity-type drain layer formed in the silicon layer being separated from the source layer with the base layer being interposed therebetween, a gate-to-drain offset layer formed between the base and drain layers, having a resistance higher than that of the base layer, and a gate electrode formed on at least a surface of the base layer via a gate insulating film wherein the silicon layer in which the base layer is formed is a strained silicon layer.

Abstract: A transistor comprises: an insulating layer; a semiconductor layer provided on a major surface of the insulating layer; a gate insulating layer provided on the base region; and a gate electrode provided on the gate insulating layer. The semiconductor layer has a source portion having a plurality of source regions of a first conductivity type and a plurality of base contact regions of a second conductivity type, the source regions being alternated with the base contact regions, a drain portion of the first conductivity type, and a base region of the second conductivity type provided between the source portion and the drain portion, the base region being in contact with the source regions and the base contact regions. A junction between the source regions and the base region is closer to the drain portion side than a junction between the base contact regions and the base region.

Abstract: A semiconductor device comprises: a first main electrode; a second main electrode; a semiconductor base region of a first conductivity type; a gate electrode provided in a trench through an insulating film, the trench being formed to penetrate the semiconductor base region; and a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type provided under the semiconductor base region. A flow of a current between the first and second main electrodes when a voltage of a predetermined direction is applied between these electrodes is controllable in accordance with a voltage applied to the gate electrode. A depleted region extends from a junction between the first and the second semiconductor regions reaching the trench.

Abstract: A MEMS (micro electro mechanical system) apparatus is equipped with a light-emitting circuit, having a light-emitting device, to emit light; a light-receiving circuit having a series circuit of series-connected light-receiving devices that receive the emitted light to generate a voltage; and a MEMS assembly driven by the generated voltage.

Abstract: A MEMS (micro electro mechanical system) apparatus is equipped with a light-emitting circuit, having a light-emitting device, to emit light; a light-receiving circuit having a series circuit of series-connected light-receiving devices that receive the emitted light to generate a voltage; and a MEMS assembly driven by the generated voltage.

Abstract: Power MISFET 20 includes SIO substrate 4 composed of first silicon substrate 1, BOX layer 2 formed on the front surface of first silicon substrate 1 and silicon substrate 3 formed on BOX layer 2. Second silicon substrate 3 is provided with lightly doped-impurity offset layer 5, P layer 6, N+ source layer 7, and N+ drain layer 8. First gate electrode 10 made of poly crystalline silicon is formed on Player 6 through gate insulation film 9. Second gate electrode 15 is formed on the back surface of first silicon substrate 1 while BOX layer 2 functions as a gate insulation film.

Abstract: The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer 4. A n-type drain layer 7 is formed in a position apart from the p-type base layer 4. On the surface of the region between the p-type base layer 4 and the n-type drain layer 7, a n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are alternately arranged from the p-type base layer 4 to the n-type drain layer 7. Further, in the region between the n-type source layer 5 and the n-type drain layer 7, a gate electrode 15 is formed via a gate insulating film 14.

Abstract: The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer 4. A n-type drain layer 7 is formed in a position apart from the p-type base layer 4. On the surface of the region between the p-type base layer 4 and the n-type drain layer 7, a n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are alternately arranged from the p-type base layer 4 to the n-type drain layer 7. Further, in the region between the n-type source layer 5 and the n-type drain layer 7, a gate electrode 15 is formed via a gate insulating film 14.