Abstract: A semiconductor storage device includes a memory cell array and first and second circuits. The memory cell array is configured to store data in a non-volatile manner. The first circuit is configured to detect a first signal from an external device that is external to the semiconductor storage device. The first signal is required when the external device communicates with the semiconductor storage device in accordance with a first interface protocol, and not required when the external device communicates with the semiconductor storage device in accordance with a second interface protocol different from the first interface protocol. The second circuit is configured to generate a second signal in a first state when the first circuit detects the first signal and in a second state when the first circuit does not detect the first signal, the second state being different from the first state.

Abstract: An improved semiconductor memory device capable of easily detecting the location of a defective bit line and a defective memory cell as a leakage current path for a short time is provided. A region flowing a leakage current no smaller than a predetermined value is determined by detecting one of a first large region and a remaining second large region, either of said first and second large regions being selected by simultaneously selecting a predetermined number of said column selection lines. Then, a region flowing a leakage current no smaller than a predetermined value is determined by detecting one of a first small region and a remaining second small region, said first and second small regions constituting said one of the first and second large regions, either of said first and second small regions being selected by simultaneously selecting a predetermined number of said column selection lines. For this purpose, an address signal output control circuit is provided within the semiconductor memory device.