Abstract: A position confirmation device is provided. The position confirmation device comprises: a registration portion, which registers event information comprising information of a place where an event is conducted; a setting portion, which sets a safety range capable of being specified as a position of a user during the event from the information of the place and a position specification accuracy of a first mode for specifying the position; an acquisition portion, which acquires position information relating to a position of a mobile terminal specified by the mobile terminal carried by the user; and a transmission portion, which transmits a switching instruction to the mobile terminal when the position indicated by the position information deviates from the safety range set by the setting portion, wherein the switching instruction instructs switching to a second mode for specifying the position by a greater power consumption and a higher accuracy than the first mode.

Abstract: A semiconductor memory device includes a first conductive layer, second conductive layers extending in a first direction and stacked above the first conductive layer in a second direction, a third conductive layer between the first conductive layer and the second conductive layers, a memory pillar extending inside the second conductive layers in the second direction, a first insulating layer that isolates the second conductive layers in a third direction, and second insulating layers spaced from an end of the first insulating layer and extending in the third direction. The second insulating layers are spaced from an extension line of the first insulating layer that extends in the first direction. The first conductive layer includes a region that overlaps in the second direction a region where extension lines of the first and second insulating layers intersect, and the third conductive layer does not overlap this intersection region in the second direction.

Abstract: The sensor node communication terminal includes: a sensor capable of collect sensor information at an installed location in autonomous timing; a control unit connected to the sensor and capable of executing calculation processing of the sensor information; a memory connected to the control unit; a wireless transmission/reception unit connected to the control unit; an antenna connected to the wireless transmission/reception unit and capable of wirelessly transmitting the sensor information or a result of the calculation processing of the sensor information; a power supply unit connected to the control unit; and a timer connected to the control unit, wherein second wireless transmission data can be received from a host side during only a predetermined time period after transmission of wireless transmission data is completed. Moreover, there is provided a wireless sensor network system to which a plurality of such sensor node communication terminals can be applied.

Abstract: A semiconductor memory device includes a first conductive layer, second conductive layers extending in a first direction and stacked above the first conductive layer in a second direction, a third conductive layer between the first conductive layer and the second conductive layers, a memory pillar extending inside the second conductive layers in the second direction, a first insulating layer that isolates the second conductive layers in a third direction, and second insulating layers spaced from an end of the first insulating layer and extending in the third direction. The second insulating layers are spaced from an extension line of the first insulating layer that extends in the first direction. The first conductive layer includes a region that overlaps in the second direction a region where extension lines of the first and second insulating layers intersect, and the third conductive layer does not overlap this intersection region in the second direction.

Abstract: A position confirmation device is provided. The position confirmation device comprises: a registration portion, which registers event information comprising information of a place where an event is conducted; a setting portion, which sets a safety range capable of being specified as a position of a user during the event from the information of the place and a position specification accuracy of a first mode for specifying the position; an acquisition portion, which acquires position information relating to a position of a mobile terminal specified by the mobile terminal carried by the user; and a transmission portion, which transmits a switching instruction to the mobile terminal when the position indicated by the position information deviates from the safety range set by the setting portion, wherein the switching instruction instructs switching to a second mode for specifying the position by a greater power consumption and a higher accuracy than the first mode.

Abstract: The sensor node communication terminal includes: a sensor capable of collect sensor information at an installed location in autonomous timing; a control unit connected to the sensor and capable of executing calculation processing of the sensor information; a memory connected to the control unit; a wireless transmission/reception unit connected to the control unit; an antenna connected to the wireless transmission/reception unit and capable of wirelessly transmitting the sensor information or a result of the calculation processing of the sensor information; a power supply unit connected to the control unit; and a timer connected to the control unit, wherein second wireless transmission data can be received from a host side during only a predetermined time period after transmission of wireless transmission data is completed. Moreover, there is provided a wireless sensor network system to which a plurality of such sensor node communication terminals can be applied.

Abstract: According to one embodiment, a semiconductor memory includes a memory cell in a memory cell array which is provided in a semiconductor substrate and which includes a first active region surrounded by a first isolation insulator, a transistor in a transistor region which is provided in the semiconductor substrate and which includes second active regions surrounded by a second isolation insulator. The second isolation insulator includes a first film, and a second film between the first film and the second active region, and the upper surface of the first film is located closer to the bottom of the semiconductor substrate than the upper surface of the second film.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes an element region, a gate insulating film, a first gate electrode, an intergate insulating film, a second gate electrode and an element isolation region. The gate insulating film is formed on the element region. The first gate electrode is formed on the gate insulating film. The intergate insulating film is formed on the first gate electrode and has an opening. The second gate electrode is formed on the intergate insulating film and in contact with the first gate electrode via the opening. The element isolation region encloses a laminated structure formed by the element region, the gate insulating film, and the first gate electrode. The air gap is formed between the element isolation region and side surfaces of the element region, the gate insulating film and the first gate electrode.

Abstract: In one embodiment, a nonvolatile semiconductor memory device includes a substrate provided with a memory cell part and sense amplifiers on a surface of the substrate, first isolation regions and first device regions disposed in the substrate under the memory cell part, and second isolation regions and second device regions disposed in the substrate under the sense amplifiers. The device further includes a plurality of interconnects disposed on the substrate in the sense amplifiers, extending in a first direction parallel to the surface of the substrate, being adjacent to one another in a second direction perpendicular to the first direction, and arranged in the same interconnect layer. At least one of the second device regions includes first and second stripe portions extending in the first direction, being adjacent in the second direction, and having stripe shapes, and a connecting portion disposed to connect the first stripe portion and the second stripe portion.

Abstract: In one embodiment, a method of manufacturing a nonvolatile semiconductor memory includes forming a plurality of memory cell transistors and a plurality of selection transistors on a substrate. The method further includes burying first and second insulators successively between memory cell transistors and between a memory cell transistor and a selection transistor, and forming the first and second insulators successively on side surfaces of selection transistors, the side surfaces facing a space between the selection transistors. The method further includes burying third to fifth insulators successively between the selection transistors via the first and second insulators. The method further includes removing the second and fourth insulators by a first etching so that the second and fourth insulators partially remain between the selection transistors.

Abstract: According to one embodiment, a semiconductor memory includes a memory cell in a memory cell array which is provided in a semiconductor substrate and which includes a first active region surrounded by a first isolation insulator, a transistor in a transistor region which is provided in the semiconductor substrate and which includes second active regions surrounded by a second isolation insulator. The second isolation insulator includes a first film, and a second film between the first film and the second active region, and the upper surface of the first film is located closer to the bottom of the semiconductor substrate than the upper surface of the second film.

Abstract: In one embodiment, a method of manufacturing a nonvolatile semiconductor memory includes forming a plurality of memory cell transistors and a plurality of selection transistors on a substrate. The method further includes burying first and second insulators successively between memory cell transistors and between a memory cell transistor and a selection transistor, and forming the first and second insulators successively on side surfaces of selection transistors, the side surfaces facing a space between the selection transistors. The method further includes burying third to fifth insulators successively between the selection transistors via the first and second insulators. The method further includes removing the second and fourth insulators by a first etching so that the second and fourth insulators partially remain between the selection transistors.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes memory transistors, an interlayer insulating film, a peripheral transistor and a sidewall. The memory transistors are formed on a semiconductor substrate. Each of the memory transistors includes a first stack gate which includes a floating gate electrode, a second gate insulating film, and a control gate electrode. The interlayer insulating film is formed between the first stack gates. The interlayer insulating film includes a first air gap. The peripheral transistor is formed on the substrate. The peripheral transistor includes a second stack gate which includes a first gate electrode, a third gate insulating film, and a second gate electrode. The sidewall is formed on a side surface of the second stack gate and includes a second air gap. An upper end of the second air gap is located at a position lower than the third gate insulating film.

Abstract: A semiconductor memory device includes a plurality of memory cell arrays each includes a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure, a first well formed in the semiconductor substrate and having a first conductivity type, an element isolation insulating film including a bottom surface shallower than a bottom surface of the first well in the first well, and buried in the semiconductor substrate, a second well including a bottom surface shallower than the bottom surface of the first well in the first well, formed along a bottom surface of at least a portion of the element isolation insulating film, and made of an impurity having a second conductivity type, and a contact line electrically connected to the first well.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes an element region, a gate insulating film, a first gate electrode, an intergate insulating film, a second gate electrode and an element isolation region. The gate insulating film is formed on the element region. The first gate electrode is formed on the gate insulating film. The intergate insulating film is formed on the first gate electrode and has an opening. The second gate electrode is formed on the intergate insulating film and in contact with the first gate electrode via the opening. The element isolation region encloses a laminated structure formed by the element region, the gate insulating film, and the first gate electrode. The air gap is formed between the element isolation region and side surfaces of the element region, the gate insulating film and the first gate electrode.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes memory transistors, an interlayer insulating film, a peripheral transistor and a sidewall. The memory transistors are formed on a semiconductor substrate. Each of the memory transistors includes a first stack gate which includes a floating gate electrode, a second gate insulating film, and a control gate electrode. The interlayer insulating film is formed between the first stack gates. The interlayer insulating film includes a first air gap. The peripheral transistor is formed on the substrate. The peripheral transistor includes a second stack gate which includes a first gate electrode, a third gate insulating film, and a second gate electrode. The sidewall is formed on a side surface of the second stack gate and includes a second air gap. An upper end of the second air gap is located at a position lower than the third gate insulating film.

Abstract: According to one embodiment, a semiconductor device includes a first contact, a second contact, and an intermediate interconnection. The first contact is made of a first conductive material. The second contact is made of a second conductive material. A lower end portion of the second contact is connected to an upper end portion of the first contact. The intermediate interconnection is made of a third conductive material and isolated from the first contact and the second contact. A lower face of the intermediate interconnection is positioned higher than a lower face of the first contact. An upper face of the intermediate interconnection is positioned lower than an upper face of the second contact. A diffusion coefficient of the first conductive material with respect to the second conductive material is lower than a diffusion coefficient of the third conductive material with respect to the second conductive material.

Abstract: In one embodiment, a nonvolatile semiconductor memory device includes a substrate provided with a memory cell part and sense amplifiers on a surface of the substrate, first isolation regions and first device regions disposed in the substrate under the memory cell part, and second isolation regions and second device regions disposed in the substrate under the sense amplifiers. The device further includes a plurality of interconnects disposed on the substrate in the sense amplifiers, extending in a first direction parallel to the surface of the substrate, being adjacent to one another in a second direction perpendicular to the first direction, and arranged in the same interconnect layer. At least one of the second device regions includes first and second stripe portions extending in the first direction, being adjacent in the second direction, and having stripe shapes, and a connecting portion disposed to connect the first stripe portion and the second stripe portion.

Abstract: A semiconductor memory device includes a plurality of memory cell arrays each includes a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure, a first well formed in the semiconductor substrate and having a first conductivity type, an element isolation insulating film including a bottom surface shallower than a bottom surface of the first well in the first well, and buried in the semiconductor substrate, a second well including a bottom surface shallower than the bottom surface of the first well in the first well, formed along a bottom surface of at least a portion of the element isolation insulating film, and made of an impurity having a second conductivity type, and a contact line electrically connected to the first well.

Abstract: A mobile communications system includes a base station that allocates a plurality of pairs of transmission and reception slots to one data frame and a portable terminal that communicates with the base station. At least two pairs of slots are allocated to one portable terminal so that one pair is used to continue a communication session and the other is used to control channels in order to secure a channel for the communication session. The portable terminal detects whether the communication condition is poorer than a first level and whether it is poorer than a second level that is lower than the first level. During a communication session, when the communication condition drops below the first level, the portable terminal requests another base station to newly establish a traffic channel, and, when the communication condition drops below the second level, it switches from the currently used traffic channel to the newly established traffic channel.