Abstract: A bad sector is detected by activating a bad sector detecting function of a recording apparatus at a predetermined interval. The bad sector is recovered, when the bad sector is detected at the detecting, by overwriting data on the bad sector with a duplication of the data, and when overwriting fails, by writing the duplication of the data on other sector.

Abstract: A decoded picture and parameters of a sequence layer, a GOP layer and a picture layer respectively for displaying the decoded picture are stored as a set in each of picture banks and parameter banks of a frame memory. Parameters of each layer stored as a set with a picture decoded immediately before are read out. Parameters attached to a picture to be decoded are decoded overwritten. Thus, the parameters of each layer stored as a set with the picture to be decoded are generated.

Abstract: In a storage system, a plurality of RAID devices are connected to a network, and data is multiplexed to primary data and secondary data by being mirrored among the RAID devices. When a failure of a disk device that can be recovered within the devices owing to the RAID configuration occurs, data of a disk device corresponding to the failed disk device is requested to a RAID device that is its mirror target and the transferred data is written to a spare disk device for the recovery. At the time of the data recovery, an access right to a group of disk devices constituting RAID and an access right to individual disk devices are exclusively controlled with respect to an input and output of the primary data.

Abstract: An input data signal string I is temporarily stored in an input register, and is input to a parallel adder operating according to the instruction of a control unit. The control unit designates an address of a ROM storing a check matrix H, and obtains information about locations of “1s” in a specific column of the check matrix corresponding to a current input data bit. The ROM instructs selectors SEL1#1–SEL1#CW to select from a register reg(M) bits corresponding to rows in which the check matrix value is 1 for the specified matrix column and sends the selected values to the adder. Results of the additions and the values output from the reg(M) are selected between for input to the reg(M) through the selectors SEL2#1–SEL2#M. This process is repeated until all the input bits have been processed.

Abstract: In an image conversion method and apparatus, luminance Y3 of each pixel of a converted image is obtained by use of an expression Y3=C1Y1+C2Y2 and from luminance Y1 of a corresponding pixel of a source image, luminance Y2 of a corresponding pixel of a low frequency image, and C1 and C2 which are functions of the luminance Y2. Since C1+C2 is constant when Y2?T2, contrast of a low frequency component can be prevented from decreasing. In a portion in which the luminance Y2 of the low frequency image is low, the low frequency image is enhanced. In a portion in which the luminance Y2 of the low frequency image is high, the low frequency image is suppressed. In a method and apparatus for detecting noise level of an original signal in real time, a plurality of local regions are set on an input image in such a manner that the local regions are distributed uniformly over the entire area of an image. In each local region, determination as to whether or not luminance is saturated is performed.

Abstract: A detecting circuit detects a boundary in a bit stream which is coded in compliance with a predetermined rule. The boundary is a point at which discontinuity of reproduction time occurs. An inverting circuit inverts a specific bit in a header of a succeeding bit stream immediately subsequent to the boundary, in response to the detection of the boundary by the detecting circuit. The boundary can thus be detected easily by simply monitoring the specific bit, for example, in outputting the decoded bit streams. This consequently facilitates synchronous management and the like of the bit streams. The specific bit is included in the bit stream. Thus, detecting the specific bit allows simple and accurate detection of the boundary at which discontinuity of the reproduction time occurs.

Abstract: An apparatus for reproducing video and audio includes a video decoder which receives video data coded by a unit of a first time length, an audio decoder which receives audio data coded by a unit of a second time length different from the first time length, and a synchronization control unit which suspends video output of said video decoder and audio output of said audio decoder, and resumes the audio output a certain time period after resuming the video output where the certain time period corresponds to a period from the suspension of the video output to the suspension of the audio output.

Abstract: There are connected a plurality of hosts 1 to L, a plurality of targets 1 to M and a plurality of initiators 1 to N, through a network. Each target has a managing unit which decides by itself the target search information broadcast from the initiator onto the network. In the case it is suited for data storage in the own target, data storage response information containing accepted priority information is broadcast onto the network. The target largest in priority value is notified of target selection from the initiator, thus effecting data storage.

Abstract: A record reproduction apparatus includes an encoding unit that encodes sector data to be written into a recording medium, by dividing the data into a predetermined number of blocks, and an iterative decoding unit that iteratively decodes the sector data read from the recording medium, by dividing the sector data into the predetermined number of blocks.

Abstract: Crosstalk between tracks, land prepit leakage, and effects of recording power modulation can cause the wobble signal period to change irregularly, thereby producing jitter in the recording clock which is derived by frequency multiplying the wobble signal. This problem is resolved by a recording clock generating circuit having an arrangement to average the wobble signal period, a timer for generating a rectangular wave with substantially the same period as the average period, and a frequency multiplying PLL for multiplying the timer output. The period averaging arrangement in particular determines the approximate average period at every wobble period and reflects the phase difference between the wobble signal and the timer in the timer setting so as to improve recording clock stability.

Abstract: The present invention relates to a system capable of carrying out efficient and stable system operation control even if a usage rate of the entire system varies under a situation in which the characteristics of storage units, such as maximum available total capacity and speed performance, are largely different from each other. Therefore, the system according to the present invention is composed of a monitor unit for monitoring information on a total volume of data stored in each of the storage units or in all the storage units, an index value calculating unit for calculating an index value on the basis of the monitor result and a location unit for distributively locating or relocating logical storage areas in physical storage areas on a plurality of storage units on the basis of the calculated index value.

Abstract: A detecting circuit detects a boundary in a bit stream which is coded in compliance with a predetermined rule. The boundary is a point at which discontinuity of reproduction time occurs. An inverting circuit inverts a specific bit in a header of a succeeding bit stream immediately subsequent to the boundary, in response to the detection of the boundary by the detecting circuit. The boundary can thus be detected easily by simply monitoring the specific bit, for example, in outputting the decoded bit streams. This consequently facilitates synchronous management and the like of the bit streams. The specific bit is included in the bit stream. Thus, detecting the specific bit allows simple and accurate detection of the boundary at which discontinuity of the reproduction time occurs.

Abstract: An input signal data string I is temporarily stored in a register, and is input to an adder according to the instruction of a control unit. The control unit designates a ROM storing a check matrix H and obtains information about a position, in which 1 is stored in a specific column of the check matrix. The ROM instructs SEL1#1 through #CW to select a value corresponding the position, in which the check matrix is 1 from values from reg(M) using a selector SELL and sends it to an adder. If the result of an addition is selected by a selector SEL2 instructed to select it by the ROM, then it is input to the reg(M). If no addition has been applied, the value output from the reg(M) is input to the reg (M) again through the selector SEL2. This process is repeated until all the operations have finished.

Abstract: In an image conversion method and apparatus, luminance Y3 of each pixel of a converted image is obtained by use of an expression Y3=C1Y1+C2Y2 and from luminance Y1 of a corresponding pixel of a source image, luminance Y2 of a corresponding pixel of a low frequency image, and C1 and C2 which are functions of the luminance Y2. Since C1+C2 is constant when Y2≦T2, contrast of a low frequency component can be prevented from decreasing. In a portion in which the luminance Y2 of the low frequency image is low, the low frequency image is enhanced. In a portion in which the luminance Y2 of the low frequency image is high, the low frequency image is suppressed. In a method and apparatus for detecting noise level of an original signal in real time, a plurality of local regions are set on an input image in such a manner that the local regions are distributed uniformly over the entire area of an image. In each local region, determination as to whether or not luminance is saturated is performed.

Abstract: A video decoding device which enables smooth reverse playback of 3:2 pulldown video streams. A video data storage unit stores pictures constituting a video stream that is being played back, where each picture consists of a first field and a second field. An attribute data storage unit stores attribute data which describes how each picture should be displayed. The attribute data includes a repeat-first-field flag for each picture. When playing back the video stream in a reverse direction, a reverse playback unit determines whether the repeat-first-field flag is set or cleared, and reads out the first and second fields of each picture in the same order as that in forward playback mode if the repeat-first-field flag is set. If the repeat-first-field flag is cleared, it reads out the first and second fields in the opposite order to that in the forward playback mode.

Abstract: A moving picture decoding apparatus includes an input part which adds at least one picture tag to a bit stream, having a plurality of pictures, which has been subjected to intraframe or interframe encoding, the picture tag or tags having a value monotonously changing on a picture-by-picture basis, independent of picture content, a buffer memory storing the bit stream and a controller controlling one or more of the plurality of pictures stored in the buffer memory by referring to the corresponding picture tag or tags.

Abstract: A moving picture decoding apparatus includes an input part which provides a picture tag to a bit stream which has been subjected to intraframe or interface encoding, the picture tag having a value monotonously changing on a picture base. A buffer memory stores the bit stream. A controller controls a number of pictures stored in the buffer memory by referring to the picture tag.

Abstract: Crosstalk between tracks, land prepit leakage, and effects of recording power modulation can cause the wobble signal period to change irregularly, producing jitter in the recording clock derived by frequency multiplying the wobble signal. This problem is resolved by a recording clock generating circuit having an arrangement to average the wobble signal period, a timer for generating a rectangular wave with substantially the same period as the average period, and a frequency multiplying PLL for multiplying timer output. The period averaging arrangement in particular determines the approximate average period at every wobble period and reflects the phase difference between the wobble signal and timer in the timer setting to improve recording clock stability.

Abstract: A display parameter synchronous holding circuit 20 comprises a register group 21 for receiving display parameters DP separated by variable length decoding circuit, a selector 24 for selecting and outputting either the display parameters DP or the output of the register group 21, register group 22 for receiving the output of the selector 24, a register group 23 for storing the output of the register group 22 in response to VSYNC, and a control circuit 25 for causing the selector 24 to select the output of the register group 21 and making latch signals SH2 and SH1 to register groups 22 and 21 active in the order when the picture coding type PCT indicates I-picture or P-picture, and for causing the selector 24 to select DP and making SH2 active when PCT indicates B-picture.

Abstract: A display parameter synchronous holding circuit 20 comprises a register group 21 for receiving display parameters DP separated by variable length decoding circuit, a selector 24 for selecting and outputting either the display parameters DP or the output of the register group 21, register group 22 for receiving the output of the selector 24, a register group 23 for storing the output of the register group 22 in response to VSYNC, and a control circuit 25 for causing the selector 24 to select the output of the register group 21 and making latch signals SH2 and SH1 to register groups 22 and 21 active in the order when the picture coding type PCT indicates I-picture or P-picture, and for causing the selector 24 to select DP and making SH2 active when PCT indicates B-picture.