Patents by Inventor Mitsuhiko Okutsu
Mitsuhiko Okutsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080309383Abstract: A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.Type: ApplicationFiled: April 21, 2008Publication date: December 18, 2008Inventors: Naoki Yada, Yasuyuki Saito, Yasushi Shibatsuka, Katsunori Koike, Mitsuhiko Okutsu
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Patent number: 7382681Abstract: A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.Type: GrantFiled: February 21, 2007Date of Patent: June 3, 2008Assignees: Renesas Technology Corp., Hitachi Engineering Co., Ltd.Inventors: Naoki Yada, Yasuyuki Saito, Yasushi Shibatsuka, Katsunori Koike, Mitsuhiko Okutsu
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Publication number: 20070159914Abstract: A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.Type: ApplicationFiled: February 21, 2007Publication date: July 12, 2007Inventors: Naoki Yada, Yasuyuki Saito, Yasushi Shibatsuka, Katsunori Koike, Mitsuhiko Okutsu
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Patent number: 7196967Abstract: A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.Type: GrantFiled: June 5, 2006Date of Patent: March 27, 2007Assignees: Renesas Technology Corp., Hitachi Engineering Co., Ltd.Inventors: Naoki Yada, Yasuyuki Saito, Yasushi Shibatsuka, Katsunori Koike, Mitsuhiko Okutsu
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Patent number: 7193929Abstract: A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.Type: GrantFiled: June 5, 2006Date of Patent: March 20, 2007Assignees: Renesas Technology Corp., Hitachi Engineering Co., Ltd.Inventors: Naoki Yada, Yasuyuki Saito, Yasushi Shibatsuka, Katsunori Koike, Mitsuhiko Okutsu
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Publication number: 20060238216Abstract: A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.Type: ApplicationFiled: June 5, 2006Publication date: October 26, 2006Inventors: Naoki Yada, Yasuyuki Saito, Yasushi Shibatsuka, Katsunori Koike, Mitsuhiko Okutsu
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Patent number: 7126872Abstract: In view of controlling overshoot when the power supply is inputted without increase in the area occupied with a chip in a voltage generating circuit mounted over a semiconductor integrated circuit, an internal voltage generating circuit comprises a voltage generating circuit for generating a second voltage from a first voltage supplied from outside, and an output buffer for generating a third voltage corresponding to the second voltage. The third voltage is used as the operation power supply of the internal circuit. Moreover, a first switch for enabling an output node of the second voltage to become conductive to the predetermined potential and a control circuit for turning ON the first switch for the predetermined period in response to input of the first voltage are also provided. An output terminal of the output buffer is not clamped but an output of the voltage generating circuit in the preceding stage is clamped to the predetermined voltage.Type: GrantFiled: October 12, 2004Date of Patent: October 24, 2006Assignee: Renesas Technology Corp.Inventors: Kenichi Fukui, Mitsuru Hiraki, Mitsuhiko Okutsu
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Publication number: 20060227650Abstract: A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.Type: ApplicationFiled: June 5, 2006Publication date: October 12, 2006Inventors: Naoki Yada, Yasuyuki Saito, Yasushi Shibatsuka, Katsunori Koike, Mitsuhiko Okutsu
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Patent number: 7061825Abstract: A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.Type: GrantFiled: June 15, 2004Date of Patent: June 13, 2006Assignees: Renesas Technology Corp., Hitachi Engineering Co., Ltd.Inventors: Naoki Yada, Yasuyuki Saito, Yasushi Shibatsuka, Katsunori Koike, Mitsuhiko Okutsu
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Publication number: 20050083736Abstract: In view of controlling overshoot when the power supply is inputted without increase in the area occupied with a chip in a voltage generating circuit mounted over a semiconductor integrated circuit, an internal voltage generating circuit comprises a voltage generating circuit for generating a second voltage from a first voltage supplied from outside, and an output buffer for generating a third voltage corresponding to the second voltage. The third voltage is used as the operation power supply of the internal circuit. Moreover, a first switch for enabling an output node of the second voltage to become conductive to the predetermined potential and a control circuit for turning ON the first switch for the predetermined period in response to input of the first voltage are also provided. An output terminal of the output buffer is not clamped but an output of the voltage generating circuit in the preceding stage is clamped to the predetermined voltage.Type: ApplicationFiled: October 12, 2004Publication date: April 21, 2005Inventors: Kenichi Fukui, Mitsuru Hiraki, Mitsuhiko Okutsu
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Publication number: 20050047265Abstract: A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.Type: ApplicationFiled: June 15, 2004Publication date: March 3, 2005Inventors: Naoki Yada, Yasuyuki Saito, Yasushi Shibatsuka, Katsunori Koike, Mitsuhiko Okutsu
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Patent number: 6512413Abstract: A voltage boost circuit operates by applying a power supply voltage to both terminals of a booster capacitance in a discharge period; and, in a charging period which follows the discharge period, by turning on a switching circuit in response to application of one shot pulse thereto, a power supply voltage is applied to one terminal of said booster capacitance, a ground potential is applied to the other one terminal thereof, wherein, during the charging of said booster capacitance, a pulse width of the one shot pulse is adjusted in accordance with a magnitude of the power supply voltage.Type: GrantFiled: May 28, 2002Date of Patent: January 28, 2003Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Mitsuhiko Okutsu, Shoji Sato
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Publication number: 20020140499Abstract: A voltage boost circuit operates by applying a power supply voltage to both terminals of a booster capacitance in a discharge period; and, in a charging period which follows the discharge period, by turning on a switching circuit in response to application of one shot pulse thereto, a power supply voltage is applied to one terminal of said booster capacitance, a ground potential is applied to the other one terminal thereof, wherein, during the charging of said booster capacitance, a pulse width of the one shot pulse is adjusted in accordance with a magnitude of the power supply voltage.Type: ApplicationFiled: May 28, 2002Publication date: October 3, 2002Inventors: Mitsuhiko Okutsu, Shoji Sato
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Patent number: 6433623Abstract: A voltage boost circuit operates by: applying a power supply voltage to both terminals of a booster capacitance in a discharge period; and in a charging period which follows the discharge period, by turning on a switching circuit in response to application of one shot pulse thereto, a power supply voltage is applied to one terminal of said booster capacitance, a ground potential is applied to the other one terminal thereof, wherein, during the charging of the booster capacitance, a pulse width of said one shot pulse is adjusted in accordance with a magnitude of the power supply voltage.Type: GrantFiled: October 20, 1999Date of Patent: August 13, 2002Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Mitsuhiko Okutsu, Shoji Sato
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Patent number: 5148049Abstract: A driving circuit suitable for driving a capacitive load such as an EL display panel is disclosed, which comprises a first power source terminal; a second power source terminal; an output terminal, with which a capacitive load is connected; a source side thyristor connected between the first power source terminal and the output terminal, and supplying current to the load; a sink side thyristor connected between the second power source terminal and the output terminal and drawing-out current from the load; and a control section connected between the first power source terminal and the second power source terminal and ON-OFF controlling the source side thyristor and the sink side thyristor through a circuit arrangement coupled between the control circuit and the gates of the thyristors.Type: GrantFiled: September 11, 1989Date of Patent: September 15, 1992Assignees: Hitachi, Ltd., Hitachi Engineering Ltd.Inventors: Mitsuhiko Okutsu, Kenji Abe, Tadaaki Kariya
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Patent number: 4967100Abstract: A capacitive load driving apparatus which has a plurality of first switching elements connected between a plurality of parallel loads and a first power source terminal for switching currents which charge the loads. There is furthermore provided a plurality of bipolar transistors connected between connecting points (of the first switching elements and the loads) and a second power source terminal for discharging charges stored in the loads and a plurality of second switching elements connected between a third power source terminal and bases of the bipolar transistor, respectively, for switching base currents supplied from the third power source terminal to the bipolar transistors.Type: GrantFiled: December 20, 1988Date of Patent: October 30, 1990Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.Inventors: Mitsuhiko Okutsu, Tadaaki Kariya, Kouji Kawamoto, Syuzoh Kaneko, Yasuhiro Mashiko
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Patent number: 4733106Abstract: A device for driving a capacitive load, comprising a first switching element responsive to an external control signal for selectively conducting a charge current therethrough to the load, a second switching element responsive to the external control signal for conducting a discharge current from the load and a generator for generating from the discharge current a cutoff signal to be applied to the first switching element to ensure turn-off of the latter.Type: GrantFiled: April 1, 1985Date of Patent: March 22, 1988Assignees: Hitachi, Ltd., Hitachi Engineering Co.Inventors: Mitsuhiko Okutsu, Tatsuo Shimura, Tadaaki Kariya
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Patent number: 4725770Abstract: A reference voltage circuit in which an output reference voltage is stabilized against variations in power source as well as in transistor current amplification factor h.sub.FE.Type: GrantFiled: February 11, 1987Date of Patent: February 16, 1988Assignees: Hitachi, Ltd., Hitachi Engineering Co.Inventors: Mitsuhiko Okutsu, Tatsuo Shimura, Tadaaki Kariya, Kazuyoshi Masuda