Abstract: Blind transport format detection with sliding window trace-back for evaluating decodings to candidate block lengths together with piecewise linear approximation of the reliability figure (logarithm of ratio of maximum survivor path metric minus minimum survivor path metric divided by 0 state path metric minus minimum survivor path metric) with a small lookup table plus simple logic.

Abstract: A direct comparison adaptive halting turbo decoder computes the sum of the a priori and the extrinsic information sequences at each iteration step. The sum sequences are coded so as to be simple binary sequences. New sum sequences are generated during each iteration and used to estimate the state of the convergence without resorting to use of transmitted error detection codes. The adaptive halting turbo decoder is halted when the sum sequences generated in a single iteration step produce identical binary sequences, i.e. a change in the sum sequence is observed during the iteration and when there is no more change, the iteration is halted.

Abstract: A CRC-based adaptive halting turbo decoder applies a CRC code to identify internally generated information sequences. The information sequences are encoded with the CRC code and can be substantially identified by only the parity part. New information sequences are generated during each iteration and used to estimate the state of the convergence. The CRC-based adaptive halting turbo decoder is halted when the information sequences generated in two contiguous iterations produce identical parity bits. Memory storage requirements for the adaptive halting are reduced since only the parity bits are stored.

Abstract: Blind transport format detection with sliding window trace-back for evaluating decodings to candidate block lengths together with piecewise linear approximation of the reliability logarithm function with a small lookup table plus simple logic.

Abstract: Blind transport format detection with sliding window trace-back for evaluating decodings to candidate block lengths together with piecewise linear approximation of the reliability logarithm function with a small lookup table plus simple logic.

Abstract: A circuit is designed with an encoder circuit (602) coupled to receive a data sequence. The encoder circuit produces a first encoded data sequence and a second encoded data sequence from the data sequence. A first spreading circuit (606) is coupled to receive the data sequence and the first encoded data sequence. The first spreading circuit produces a first modulated data sequence in response to a first code. A second spreading circuit (614) is coupled to receive the data sequence and the second encoded data sequence. The second spreading circuit produces a second modulated data sequence in response to a second code.