Abstract: An optical disk apparatus according to the invention comprises a housing, a tray retractably mounted in the housing, and a bezel 10 adapted to close an opening of the housing 2 when the tray is accommodated in the housing 2. An electrically conductive metallic member 15 is disposed in at least one of main flat portions in the bezel 10. When the tray is accommodated in the housing, at least one surface of the conductive metallic member 15 is in contact with the housing.

Abstract: An apparatus to be inspected is mounted on one surface of a socket board. An auxiliary inspecting apparatus for adjusting timing of write signals transmitted from a semiconductor inspecting apparatus is mounted on the other surface of the socket board. Input/output (I/O) pins of the auxiliary inspecting apparatus are connected to corresponding I/O pins of the inspected device via through holes in the socket board on a one-to-one basis. This semiconductor inspecting method is thus capable of easily suppressing the delay difference between a plurality of signals output from the semiconductor inspecting apparatus.

Abstract: Row faulty bit storage memory corresponding to a spare row circuit and a column faulty bit storage memory corresponding to a spare column circuit are provided independently of each other, and faulty bits of these faulty bit storage memories are counted by a row faulty bit counter and a column faulty bit counter, respectively. Repairability of the faulty row and repairability of the faulty column are determined using the row faulty bit storage memory and the column faulty bit storage memory. A time required for determining repairability of the faulty bit of a semiconductor memory is reduced, and a storage capacity of the faulty bit storage memory is reduced.

Abstract: An apparatus to be inspected is mounted on one surface of a socket board. An auxiliary inspecting apparatus for adjusting timing of write signals transmitted from a semiconductor inspecting apparatus is mounted on the other surface of the socket board. Input/output (I/O) pins of the auxiliary inspecting apparatus are connected to corresponding I/O pins of the inspected device via through holes in the socket board on a one-to-one basis. This semiconductor inspecting method is thus capable of easily suppressing the delay difference between a plurality of signals output from the semiconductor inspecting apparatus.

Abstract: A first delay circuit for delaying a data signal IND output from a memory circuit and a second delay circuit for delaying a strobe signal INS, and a latch circuit for latching data according to the outputs of the first and the second delay circuits are provided as a test circuit inside a DDR SDRAM. A tester can observe results of latching by the latch circuit to facilitate determination whether the data signal and the strobe signal have a correlation adapted to a standard. Accordingly, such a DDR SDRAM can be provided that is capable of conducting an examination whether the device meets a tDQSQ standard defining a correlation between the strobe signal DQS and the data signal DQ with ease.

Abstract: A first delay circuit for delaying a data signal IND output from a memory circuit and a second delay circuit for delaying a strobe signal INS, and a latch circuit for latching data according to the outputs of the first and the second delay circuits are provided as a test circuit inside a DDR SDRAM. A tester can observe results of latching by the latch circuit to facilitate determination whether the data signal and the strobe signal have a correlation adapted to a standard. Accordingly, such a DDR SDRAM can be provided that is capable of conducting an examination whether the device meets a tDQSQ standard defining a correlation between the strobe signal DQS and the data signal DQ with ease.

Abstract: In a semiconductor device including banks A and B, testing and redundancy analysis of the bank B are first carried out by using a conventional tester, and redundancy replacement is carried out. Then, the bank A is tested by a BIST circuit and the test result of each bit is written to the bank B. By using the bank B as a memory for defect analysis, a tester connected to the semiconductor device while testing the bank A does not need a large capacity analysis memory. Thus, an inexpensive redundancy analysis system can be provided.

Abstract: A semiconductor integrated circuit device includes a plurality of ECL gate groups. Each gate group includes a plurality of ECL gates each having a constant current source formed by a MOS transistor circuit. Each gate group also includes one gate voltage control circuit. When the gate voltage control circuit receives a signal indicating a selection state for the group, it applies a high potential bias voltage to the MOS transistor circuits of all the ECL gates within the gate group. On the other hand, when it receives a signal indicating a non-selection state, it applies a low potential bias voltage (GND potential) to them, thereby lowering the constant current to the minimum necessary amount. The circuit is capable of largely saving the current consumption by controlling the bias voltage for the MOS transistor circuits in two steps depending on the selection state or the non-selection state.

Abstract: A semiconductor memory device with a redundant configuration according to the present invention includes a roll call circuit which turns an output signal of a sense amplifier compulsorily to a signal of a predetermined logical level when a portion constituting the redundant configuration is accessed, and turns an output signal of the output control circuit to that of the same predetermined logical level when a write instruction is given outside a normal level. Whether a spare memory cell is accessed can be checked in every output and the redundant configuration can operate with stability.

Abstract: In a test of a fabricated semiconductor memory chip, a test control signal is supplied to a test control circuit, so that a spare memory cell array is tested whether spare memory cells are functionable for writing and reading of data. The test control signal is applied to terminals which are used for the supplying of an address signal, etc. For this purpose, the test control signal has a level different from that of the address signal. Therefore, the spare memory cell array can be tested simultaneously with a test of normal memory cell array.