Abstract: Impedance mismatching to be caused in signal transmission paths is reduced, without any restriction being put on the number of layers. An interconnect board according to an embodiment of the present technique includes: interconnect layers and insulating layers that are alternately stacked; vias that electrically connect the interconnect layers; front-surface-side electrode pads formed on the front-surface side; back-surface-side electrode pads that are formed on the back-surface side and are arranged in an array; and a conductor loop that is formed in a conductor path connecting one of the front-surface-side electrode pads and one of the back-surface-side electrode pads, the conductor loop being formed with interconnects in the interconnect layers and the vias, the conductor loop extending in a direction perpendicular to the thickness direction of the interconnect board.

Abstract: A package substrate includes: a first conductive layer having plural first terminal pattern portions connected to a semiconductor part loaded on a first principal surface through plural first external connection conductors, which is formed on the first principal surface; a second conductive layer having plural second terminal patterns connected to a system substrate mounted on a second principal surface opposite to the first principal surface through a second external connection conductor, which is formed on the second principal surface; an intermediate conductive layer formed between the first conductive layer and the second conductive layer; interlayer insulating layers formed between the first conductive layer and the intermediate conductive layer as well as between the second conductive layer and the intermediate conductive layer; and plural interlayer connection conductors stacked for connecting between the first conductive layer and the second conductive layer so as to pierce through the interlayer insu

Abstract: A package substrate includes: a first conductive layer having plural first terminal pattern portions connected to a semiconductor part loaded on a first principal surface through plural first external connection conductors, which is formed on the first principal surface; a second conductive layer having plural second terminal patterns connected to a system substrate mounted on a second principal surface opposite to the first principal surface through a second external connection conductor, which is formed on the second principal surface; an intermediate conductive layer formed between the first conductive layer and the second conductive layer; interlayer insulating layers formed between the first conductive layer and the intermediate conductive layer as well as between the second conductive layer and the intermediate conductive layer; and plural interlayer connection conductors stacked for connecting between the first conductive layer and the second conductive layer so as to pierce through the interlayer insu