Patents by Inventor Mitsuhiro Hirano

Mitsuhiro Hirano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10604839
    Abstract: A substrate processing apparatus, including: a processing chamber having a first and a second processing regions; a substrate mounting table rotatably installed in the processing chamber on which a substrate is mounted, and a rotation instrument configured to rotate the substrate mounting table such that the substrate passes through the first processing region and the second processing region in this order, at least one of the first and the second processing regions including: a gas supply part including a line-shaped opening portion extending in a radial direction of the substrate mounting table and configured to supply a gas from the opening portion into the region; and a gap holding member protruding from a ceiling of the processing chamber opposing the substrate, around the opening portion, toward the substrate such that a space on the substrate has a predetermined gap to serve as a passage of the supplied gas.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: March 31, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Tetsuaki Inada, Yuichi Wada, Mitsunori Ishisaka, Mitsuhiro Hirano, Sadayoshi Horii, Hideharu Itatani, Satoshi Takano, Motonari Takebayashi
  • Publication number: 20160053373
    Abstract: A substrate processing apparatus, including: a processing chamber having a first and a second processing regions; a substrate mounting table rotatably installed in the processing chamber on which a substrate is mounted, and a rotation instrument configured to rotate the substrate mounting table such that the substrate passes through the first processing region and the second processing region in this order, at least one of the first and the second processing regions including: a gas supply part including a line-shaped opening portion extending in a radial direction of the substrate mounting table and configured to supply a gas from the opening portion into the region; and a gap holding member protruding from a ceiling of the processing chamber opposing the substrate, around the opening portion, toward the substrate such that a space on the substrate has a predetermined gap to serve as a passage of the supplied gas.
    Type: Application
    Filed: August 14, 2015
    Publication date: February 25, 2016
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Tetsuaki INADA, Yuichi WADA, Mitsunori ISHISAKA, Mitsuhiro HIRANO, Sadayoshi HORII, Hideharu ITATANI, Satoshi TAKANO, Motonari TAKEBAYASHI
  • Patent number: 9111972
    Abstract: The sizes required for maintenance are reduced and an occupying floor area is reduced. The substrate processing apparatus contains a load lock chamber 41 and a transfer chamber 24 respectively provided in order from the rear side within a case 11; and a processing chamber 53 provided above the load lock chamber 41 for processing wafers 1. An opening section 27A, and an opening and closing means 28A for opening and closing the opening section 27A are respectively provided in a location at the rear side of the transfer chamber 24 where the load lock chamber 41 is not arranged.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: August 18, 2015
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Mitsunori Takeshita, Tomoyuki Matsuda, Mitsuhiro Hirano, Akihiro Sato, Shinya Morita, Toshimitsu Miyata, Koji Shibata
  • Patent number: 8816759
    Abstract: An electric circuit includes a delayed clock generation circuit to which a first clock is supplied and which is configured to generate a first delayed clock and a second delayed clock, the first delayed clock being the first clock delayed by a first delay amount, and the second delayed clock being the first clock delayed by a second delay amount different from the first delay amount, an OR gate configured to receive the first clock, the first delayed clock, and the second delayed clock as inputs and to output a second clock, and a scan circuit to which the second clock is supplied.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: August 26, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Mitsuhiro Hirano, Shuji Hamada
  • Publication number: 20140184298
    Abstract: An electric circuit includes a delayed clock generation circuit to which a first clock is supplied and which is configured to generate a first delayed clock and a second delayed clock, the first delayed clock being the first clock delayed by a first delay amount, and the second delayed clock being the first clock delayed by a second delay amount different from the first delay amount, an OR gate configured to receive the first clock, the first delayed clock, and the second delayed clock as inputs and to output a second clock, and a scan circuit to which the second clock is supplied.
    Type: Application
    Filed: October 25, 2013
    Publication date: July 3, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Mitsuhiro Hirano, Shuji Hamada
  • Patent number: 7660753
    Abstract: In a safety stock control system, safety stock is changed in response to updating of a setting value so as to be continuously maintained as a proper value. The safety stock control system is comprised of a demand prediction means, an actual value calculating means, a predicted remainder calculating means, a parameter calculating means, and a safety stock calculating means for calculating safety stock based upon a parameter calculated by the parameter calculating means. In response to updating of the setting value, data of an area, which is different from such a data read when a plan is made, is temporarily read from a data storage means to the respective means, and then, various sorts of calculating process operations are carried out either one time or plural times.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: February 9, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Toshiyuki Sakuma, Mitsuhiro Enomoto, Hideyuki Sasaki, Yuichi Kaneko, Mitsuhiro Hirano
  • Patent number: 7516383
    Abstract: An extracting unit extracts unprocessed capturing destination in a circuit. A tracing unit traces an output branch point from a capturing destination and a determining unit determines an estimated failure site and a non-failure site in the circuit. A detecting unit narrows down an estimated failure site using a fail address. It is determined whether an identifying unit has identified a failure site. If the failure site has not been identified, a delay failure simulation is performed and a comparing unit compares the comparison result of the tester measurement and the result in the delay failure simulation to determine consistency between the results. The identifying unit identifies the failure site based on the consistency.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: April 7, 2009
    Assignee: Fujitsu Microelectronics Limited
    Inventor: Mitsuhiro Hirano
  • Publication number: 20080236488
    Abstract: The sizes required for maintenance are reduced and an occupying floor area is reduced. The substrate processing apparatus contains a load lock chamber 41 and a transfer chamber 24 respectively provided in order from the rear side within a case 11; and a processing chamber 53 provided above the load lock chamber 41 for processing wafers 1. An opening section 27A, and an opening and closing means 28A for opening and closing the opening section 27A are respectively provided in a location at the rear side of the transfer chamber 24 where the load lock chamber 41 is not arranged.
    Type: Application
    Filed: June 27, 2005
    Publication date: October 2, 2008
    Inventors: Mitsunori Takeshita, Tomoyuki Matsuda, Mitsuhiro Hirano, Akihiro Sato, Shinya Morita, Toshimitsu Miyata, Koji Shibata
  • Publication number: 20070083804
    Abstract: An extracting unit extracts unprocessed capturing destination in a circuit. A tracing unit traces an output branch point from a capturing destination and a determining unit determines an estimated failure site and a non-failure site in the circuit. A detecting unit narrows down an estimated failure site using a fail address. It is determined whether an identifying unit has identified a failure site. If the failure site has not been identified, a delay failure simulation is performed and a comparing unit compares the comparison result of the tester measurement and the result in the delay failure simulation to determine consistency between the results. The identifying unit identifies the failure site based on the consistency.
    Type: Application
    Filed: January 30, 2006
    Publication date: April 12, 2007
    Inventor: Mitsuhiro Hirano
  • Publication number: 20040059649
    Abstract: In a safety stock control system, safety stock is changed in response to updating of a setting value so as to be continuously maintained as a proper value. The safety stock control system is comprised of a demand prediction means, an actual value calculating means, a predicted remainder calculating means, a parameter calculating means, and a safety stock calculating means for calculating safety stock based upon a parameter calculated by the parameter calculating means. In response to updating of the setting value, data of an area, which is different from such a data read when a plan is made, is temporarily read from a data storage means to the respective means, and then, various sorts of calculating process operations are carried out either one time or plural times.
    Type: Application
    Filed: August 6, 2003
    Publication date: March 25, 2004
    Inventors: Toshiyuki Sakuma, Mitsuhiro Enomoto, Hideyuki Sasaki, Yuichi Kaneko, Mitsuhiro Hirano
  • Publication number: 20020111914
    Abstract: The present invention discloses a technology for providing a method in on-line shopping and the like that allows products to be delivered efficiently and with no delivery errors to intermediary establishments, e.g., convenience stores, where packages can be picked up at a location other than a user's home address. A computer is set up to mediate delivery and receives a user selection via a network regarding whether a product is to be shipped to the user's home or to another site. If another site is selected, a map of the area showing potential destinations is displayed, and the recipient makes a selection from the map. Special offers available when the package is picked up at a site are also displayed. When the recipient specifies a delivery destination, a coupon containing a recipient authentication certificate and special offers is issued.
    Type: Application
    Filed: February 1, 2002
    Publication date: August 15, 2002
    Inventors: Shuji Terada, Hideo Noyama, Takeshi Matsuki, Hiroyuki Kojima, Ryusuke Ikegami, Mitsuhiro Hirano, Mitsuru Iwamura
  • Publication number: 20020104206
    Abstract: A substrate processing apparatus comprises a substrate processing chamber for processing a substrate, a load lock chamber, a gas supply line for supplying gas into the load lock chamber, exhaust lines for exhausting the load lock chamber, a moving mechanism provided in the load lock chamber and capable of moving the substrate, local exhaust lines capable of locally exhausting dust generating portions of the moving mechanism, a flow rate controlling device provided in the gas supply line and flow rate controlling devices provided in the local exhaust lines. The flow rates of the flow rate controlling devices are monitored and controlled to control the inside pressure of the load lock chamber to be slightly higher than the atmosphere pressure, thereby preventing the backward flow from the vent line.
    Type: Application
    Filed: March 7, 1997
    Publication date: August 8, 2002
    Inventor: MITSUHIRO HIRANO
  • Publication number: 20020034305
    Abstract: According to the present invention, a service issuing system 1110 comprises identification number issuing means 1120 for issuing an identification number 1130 required to receive a service in accordance with an application from a user system 1210, encryption means 1150 for encrypting the identification number 1130 and generating encrypted data 1160 by a private key 1140 corresponding to a public key owned by a service provider, and encryption means 1170 for encrypting the encrypted data 1160 and generating encrypted data 1180 by an encryption key 1240 corresponding to a decryption key owned by the user system 1210.
    Type: Application
    Filed: July 20, 2001
    Publication date: March 21, 2002
    Inventors: Hideo Noyama, Mitsuhiro Hirano, Shuji Terada, Takeshi Matsuki, Mitsuru Iwamura
  • Patent number: 6332898
    Abstract: A substrate processing apparatus comprises a semiconductor wafer processing chamber, a wafer transfer device, a wafer cassette holding unit, a wafer cassette transfer device and a wafer cassette bringing in/out section disposed in this order and a housing. The wafer cassette holding unit is movable between a wafer processing time position and a maintenance time position thereof and the wafer cassette transfer device is movable between a wafer processing time position and a maintenance time position thereof. The wafer cassette bringing in/out section is capable of rotating forward of the housing, whereby the front face of said housing is opened.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: December 25, 2001
    Assignee: Kokusai Electric Co., Ltd.
    Inventors: Kouji Tometsuka, Mitsuhiro Hirano, Tetsuya Marubayashi
  • Patent number: 6264706
    Abstract: A substrate processing apparatus comprises a substrate processing chamber for processing a substrate, a load lock chamber, a gas supply line for supplying gas into the load lock chamber, exhaust lines for exhausting the load lock chamber, a moving mechanism provided in the load lock chamber and capable of moving the substrate, local exhaust lines capable of locally exhausting dust generating portions of the moving mechanism, a flow rate controlling device provided in the gas supply line and flow rate controlling devices provided in the local exhaust lines. The flow rates of the flow rate controlling devices are monitored and controlled to control the inside pressure of the load lock chamber to be slightly higher than the atmosphere pressure, thereby preventing the backward flow from the vent line.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: July 24, 2001
    Assignee: Kokusai Electric Co., Ltd.
    Inventor: Mitsuhiro Hirano
  • Patent number: 6143040
    Abstract: A substrate processing apparatus comprises a semiconductor wafer processing chamber, a wafer transfer device, a wafer cassette holding unit, a wafer cassette transfer device and a wafer cassette bringing in/out section disposed in this order and a housing. The wafer cassette holding unit is movable between a wafer processing time position and a maintenance time position thereof and the wafer cassette transfer device is movable between a wafer processing time position and a maintenance time position thereof. The wafer cassette bringing in/out section is capable of rotating forward of the housing, whereby the front face of said housing is opened.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: November 7, 2000
    Assignee: Kokusai Electric Co., Ltd.
    Inventors: Kouji Tometsuka, Mitsuhiro Hirano, Tetsuya Marubayashi
  • Patent number: 5810538
    Abstract: A semiconductor manufacturing equipment, which comprises a boat elevator installed below a reaction chamber for loading a boat into the reaction chamber, cassette stocker installed opposite to the boat elevator, a wafer carrier installed between the cassette stocker and the boat elevator and used for transferring wafers between the cassette stocker and the boat, and a load-lock chamber for accommodating the boat elevator, whereby wafers are carried in the atmospheric air within the semiconductor manufacturing equipment, and the transport time is set in such manner that an increase of a natural oxide film formed on the wafers is 2 angstroms or less.
    Type: Grant
    Filed: August 5, 1997
    Date of Patent: September 22, 1998
    Assignee: Kokusai Electric Co., Ltd.
    Inventors: Makoto Ozawa, Mitsuhiro Hirano
  • Patent number: 5277215
    Abstract: A plurality of airtight chambers are connected through blocking means, which can communicate or shut off the chambers, and at least one of the airtight chambers is used as a processing chamber. One of the adjacent airtight chambers is replaced by a replacement gas, and the replacement gas is supplied to the other of the adjacent airtight chambers. When pressure difference or pressure in the two adjacent airtight chambers is below a predetermined value, the adjacent two airtight chambers are communicated, and pressure in the two airtight chambers is equalized.
    Type: Grant
    Filed: January 21, 1993
    Date of Patent: January 11, 1994
    Assignee: Kokusai Electric Co., Ltd.
    Inventors: Hidehiro Yanagawa, Hiroyuki Nishiuchi, Masakazu Shimada, Mitsuhiro Hirano, Tomoshi Taniyama, Kazumi Nikaido, Yoshikazu Hisajima, Michio Sato