Abstract: An semiconductor device capable of suppressing an increase in layout area can be provided. According to one embodiment, the semiconductor device comprises a transistor including a drain formed in a main surface portion of the semiconductor substrate, a source formed in a main surface portion, and a gate for controlling the current between the drain and the source, a drain wiring connected to the drain through the contact, and a passing wire disposed between the source wiring connected to the source through the contact and insulated from the drain, the source, and the gate.

Abstract: An semiconductor device capable of suppressing an increase in layout area can be provided. According to one embodiment, the semiconductor device comprises a transistor including a drain formed in a main surface portion of the semiconductor substrate, a source formed in a main surface portion, and a gate for controlling the current between the drain and the source, a drain wiring connected to the drain through the contact, and a passing wire disposed between the source wiring connected to the source through the contact and insulated from the drain, the source, and the gate.

Abstract: A multi-layered aquaponics system used for cultivation has a fish tank, at least one layer of a grow bed adapted to support growth of at least one variety of plant in a direction substantially vertical to a plane of a backing element of the layer, a growth light system having at least one LED growth-light fixture disposed above the grow bed, a water supply system having a water circulation loop, and an aeration system without a power source. The aeration system includes a standpipe inside the layers of grow beds and a plurality of bell siphons positioned within the standpipe and connected to a water drainpipe.

Abstract: A multi-layered aquaponics system and an aquaponics cultivation method in an indoor vertical farming application are disclosed. The aquaponics cultivation method of the multi-layered aquaponic system involves using a submersible pump to drain water (through a supply pipe) from a fish tank, located at the lowest level, to each layer of plant grow-bed. When water in one particular grow-bed is filled up to the height of a standpipe of a Bell Siphon, water would drain automatically into a water drain pipe, which circulates back to the fish tank. The strong water current deploying at least one Bell Siphon in a vertical structure will give suitable aeration into the fish tank and emit no carbon by saving power in the aeration system.

Abstract: A semiconductor memory device includes a memory cell array divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns, an address pad column formed outside the memory cell array, the address pad column comprising a plurality of address pads that are arranged to be substantially parallel to the subarray columns, a data I/O pad column formed in a middle section of the memory cell array, the data I/O pad column comprising data I/O pads that are arranged to be substantially parallel to the subarray columns, an address input circuit arranged in the middle section of the memory cell array, and a pad input address line formed in a direction substantially perpendicular to the subarray columns on the memory cell array, the pad input address line directly connecting the address pad and the address input circuit.

Abstract: A semiconductor memory device includes a memory cell array divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns, an address pad column formed outside the memory cell array, the address pad column comprising a plurality of address pads that are arranged to be substantially parallel to the subarray columns, a data I/O pad column formed in a middle section of the memory cell array, the data I/O pad column comprising data I/O pads that are arranged to be substantially parallel to the subarray columns, an address input circuit arranged in the middle section of the memory cell array, and a pad input address line formed in a direction substantially perpendicular to the subarray columns on the memory cell array, the pad input address line directly connecting the address pad and the address input circuit.

Abstract: A semiconductor memory device includes a memory cell array divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns, an address pad column formed outside the memory cell array, the address pad column comprising a plurality of address pads that are arranged to be substantially parallel to the subarray columns, a data I/O pad column formed in a middle section of the memory cell array, the data I/O pad column comprising data I/O pads that are arranged to be substantially parallel to the subarray columns, an address input circuit arranged in the middle section of the memory cell array, and a pad input address line formed in a direction substantially perpendicular to the subarray columns on the memory cell array, the pad input address line directly connecting the address pad and the address input circuit.

Abstract: A semiconductor apparatus includes a cell and a dummy cell. The cell has a first conductivity type of diffusion layer formed in a second conductivity type of semiconductor region. The second conductivity type is opposite to the first conductivity type. The dummy cell has the second conductivity type of dummy diffusion layer formed in the semiconductor region. The dummy cell is adjacent to the cell.