Patents by Inventor Mitsuhiro Ishiguro

Mitsuhiro Ishiguro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6847577
    Abstract: A memory cell array is composed of a plurality of blocks separated in column direction every three word lines. Inter-block bit wires are arranged. Each inter-block bit line connects a middle diffusion wire for one of the memory cell units of first block of the separated blocks and the middle diffusion wire for one of the memory cell units of the adjacent second block lying on the other end side of the diffusion wires of the first block. Inter-block ground wires are arranged. Each inter-block ground wire connects the boundary diffusion wire for the one memory cell unit of the first block and the boundary diffusion wire for the one memory cell unit of the adjacent third block lying on the one end side of the diffusion wires of the first block.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: January 25, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Mitsuhiro Ishiguro
  • Publication number: 20040159870
    Abstract: A memory cell array is composed of a plurality of blocks separated in column direction every three word lines. Inter-block bit wires are arranged. Each inter-block bit line connects a middle diffusion wire for one of the memory cell units of first block of the separated blocks an the middle diffusion wire for one of the memory cell units of the adjacent second block lying on the other end side of the diffusion wires o the first block. Inter-block ground wires are arranged. Each inter-block ground wire connects the boundary diffusion wire for the one memory cell unit of the first block and the boundary diffusion wire for the one memory cell unit of the adjacent third block lying on the one end side of the diffusion wires of the first block.
    Type: Application
    Filed: November 12, 2003
    Publication date: August 19, 2004
    Applicant: NEC Electronics Corporation
    Inventor: Mitsuhiro Ishiguro
  • Patent number: 5878048
    Abstract: A mask ROM having a redundancy function according to the present invention comprises a plurality of redundancy memory cells subjected to data write processing using a laser trimmer, a bit line connected to each of the plurality of redundancy memory cells, a sense amplifier connected to the redundancy bit line, a redundancy bit setting section for holding a setting result, and a switch section for selectively outputting an output from the sense amplifier as it is and an inverted output thereof in accordance with the setting result.
    Type: Grant
    Filed: April 22, 1997
    Date of Patent: March 2, 1999
    Assignee: NEC Corporation
    Inventor: Mitsuhiro Ishiguro