Abstract: A power conversion apparatus includes circuitry to: generate a first command to provide a first electrical output to a motor; receive a first electrical response to the first electrical output; estimate a position of a magnetic pole of the motor based on the first electrical response; set a pulse provide condition in accordance with the estimated position of the magnetic pole; generate a second command to provide a positive electrical pulse output and a negative electrical pulse output to the motor in accordance with the pulse provide condition; receive a positive electrical response to the positive electrical pulse output and a negative electrical response to the negative electrical pulse output; calculate a magnitude difference between the positive electrical response and the negative electrical response; change the pulse provide condition to generate a modified second command when the magnitude difference is smaller than a predetermined difference level; and estimate a polarity of the magnetic pole based o

Abstract: A climbing apparatus body is supported by a main frame rotatably about a rotational shaft at one end. The climbing apparatus body is capable of taking an in-use posture in which the climbing apparatus body is inclined so that the other end is located below the one end and a folded posture in which the climbing apparatus body stands so that the other end is directed upward. A handrail is supported by the main frame. A pair of right and left banisters is attached to the climbing apparatus body and includes a portion extending toward the handrail relative to the position (perpendicular line) of the rotational shaft in the direction from the other end to the one end in the in-use posture in a side view of the climbing apparatus body.

Abstract: A climbing apparatus body is supported by a main frame rotatably about a rotational shaft at one end. The climbing apparatus body is capable of taking an in-use posture in which the climbing apparatus body is inclined so that the other end is located below the one end and a folded posture in which the climbing apparatus body stands so that the other end is directed upward. A handrail is supported by the main frame. A pair of right and left banisters is attached to the climbing apparatus body and includes a portion extending toward the handrail relative to the position (perpendicular line) of the rotational shaft in the direction from the other end to the one end in the in-use posture in a side view of the climbing apparatus body.

Abstract: A hydraulic excavator is provided with a lower traveling unit, an upper structure, an engine, a hydraulic pump, an engine compartment, a pump compartment and a plurality of filter devices. The upper structure is rotatably disposed on the lower traveling unit. The pump compartment provided on the upper structure for housing the hydraulic pump. The pump compartment has a door that allows access to an interior of the pump compartment. The filter devices, which are disposed adjacent to each other, are disposed at positions that are mutually offset in a height direction of the hydraulic excavator.

Abstract: A hydraulic excavator is provided with a lower traveling unit, an upper structure, an engine, a hydraulic pump, an engine compartment, a pump compartment and a plurality of filter devices. The upper structure is rotatably disposed on the lower traveling unit. The pump compartment provided on the upper structure for housing the hydraulic pump. The pump compartment has a door that allows access to an interior of the pump compartment. The filter devices, which are disposed adjacent to each other, are disposed at positions that are mutually offset in a height direction of the hydraulic excavator.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array includes memory cells and a word line coupling the memory cells. A determination circuit determines whether write to a first memory cell group of the word line succeeded, and whether write to a second memory cell group of the word line succeeded. A test circuit counts application of write voltage during write to the word line, compares with a threshold a difference between a count of write voltage application upon success of one of respective writes to the first and second memory cell groups and a count of write voltage application upon success of the other of respective the writes, and outputs a result of the comparison.

Abstract: According to one embodiment, a semiconductor memory storage apparatus includes an array, a sense amplifier, and a controller. The array includes a memory cell. The sense amplifier includes a first latch and a second latch. The first latch and the second latch are capable of storing a data read out from the memory cell. The controller performs a first operation, a second operation, and a third operation. In the first operation, the controller transfers an inverted data in the first latch to the first node and transfers the data in the second latch. In the second operation, the controller transfers the data in the first latch to the first node and transfers an inverted data in the second latch.

Abstract: A rotor according to an embodiment includes a cylindrical rotor core in which a plurality of magnet embedding grooves are radially arranged, ferrite magnets, and samarium-based magnets. The ferrite magnets and the samarium-base magnets are arranged in juxtaposition in a radial direction in the magnet embedding grooves provided on the rotor.

Abstract: Split cores comprising laminated iron cores each having formed thereon a tooth, and a yoke and a pole piece which are connected to the tooth at both ends thereof, and arranged and connected together into an annular shape to make a stator. Both ends of the yokes and both ends of the pole pieces are displaced in one circumferential direction by laminated iron core from a top laminated layer of the iron cores of the split cores to a bottom laminated layer of the iron cores or split cores.

Abstract: Although in a conventional permanent magnet type synchronous motor, cogging torque is reduced by displacing permanent magnets of a rotor in a circumferential direction or displacing a stator core in a circumferential direction, since the skew so produced reduces the output of the motor and moreover the winding work of windings cannot be automated to make the resulting motor highly expensive, split cores are provided which solves those problems and enables the winding work of windings to be automated so as to obtain an inexpensive and high-output motor.

Abstract: A semiconductor integrated circuit device is disclosed. The device includes a memory cell array, an I/O buffer, a read/write buffer, an error checking and correcting circuit, and an initialization checking circuit. N-bit data is input to the I/O buffer and the I/O buffer outputs N-bit data. The I/O buffer inputs N-bit data to the read/write buffer, and the read/write buffer outputs N-bit data to the I/O buffer. The memory cell array inputs up to M×N-bit data to the read/write buffer, and the read/write buffer outputs up to M×N-bit data to the memory cell array. The read/write buffer writes a variable number of bits to the memory cell array (N is a natural number equal to or larger than 1, and M is a natural number equal to or larger than 2).

Abstract: A voice coil type linear motor with a cooling function. A closed magnetic circuit formed into the ?-shape, by an inner yoke provided between a pair of outer yokes made up of magnetic materials arranged in parallel with a longitudinal center axis in such a manner as to be in parallel with the pair of outer yokes. The outer yokes and side yokes are provided at both end portions of the inner yoke. Permanent magnets are provided on inner sides of the outer yokes and on outer sides of the inner yoke with polarities thereof which face opposite surfaces of the outer yoke. The inner yoke is made opposite to each other or with polarities thereof which face only the outer yokes being made opposite each other to thereby a field. An armature made up of a bobbin of non-magnetic and insulating materials is provided. A coil is provided around the bobbin between the permanent magnets via air gaps in such a manner as to move in an axial direction or in such a manner that. The coil is wound around the bobbin.

Abstract: A semiconductor integrated circuit device includes a memory cell array, an error checking and correcting (ECC) circuit which performs an error checking and correcting operation for readout data read out from the normal data storing portion at data readout time during read latency and an I/O buffer. The memory cell array includes a normal data storing portion and a parity data storing portion. The normal data storing portion stores data for use in a normal data write and a normal data read. The parity data storing portion stores parity data for use in error checking and correcting. The EEC circuit carries out error checking and correcting read data read out from the normal data storing portion, during read latency cycle at a data read operation. The I/O buffer outputs the read data error checked and corrected by the ECC circuit, after the read latency cycle has lapsed.

Abstract: A semiconductor integrated circuit device is disclosed. The device includes a memory cell array, an I/O buffer, a read/write buffer, an error checking and correcting circuit, and an initialization checking circuit. N-bit data is input to the I/O buffer and the I/O buffer outputs N-bit data. The I/O buffer inputs N-bit data to the read/write buffer, and the read/write buffer outputs N-bit data to the I/O buffer. The memory cell array inputs up to M×N-bit data to the read/write buffer, and the read/write buffer outputs up to M×N-bit data to the memory cell array. The read/write buffer writes a variable number of bits to the memory cell array (N is a natural number equal to or larger than 1, and M is a natural number equal to or larger than 2).

Abstract: A semiconductor memory device is disclosed which comprises a cell array including a normal data section used for normal data write and read and a parity data section used for check data write and read, the check data being for execution of error check of data as read out of the normal data section, a data buffer for temporal stage of read data from the cell array and write data into the cell array, and an ECC circuit for generating the check data to be stored in the parity data section from write data as input during data writing, and for performing error check and correction of data read out of the normal section based on the data read out of the normal data section and the check data read out of said parity data section during data reading. N-bit parallel data transfer is performed between the data buffer and normal data section whereas m-bit parallel data transfer is done between the data buffer and external input/output terminals (where m and n are integers satisfying m<n).

Abstract: A small vacuum chamber is provided which needs no load lock chamber. In a voice coil type linear motor including a closed magnetic circuit formed into the ?-shape, by a pair of outer yokes (11), an inner yoke (12) and side yokes (13) and in which an armature is fixed to an inner side of the outer yoke (11), whereas permanent magnet sides are allowed to move, a coil (18) is wound around a bobbin (17), an exterior case 23 for the bobbin is constructed so as to make a coil portion watertight, and a fluid supply port and a fluid discharge port are provided either on the bobbin or on the case, whereby a cooling fluid is made to flow between the coil and the case so as to cool the coil directly.

Abstract: A semiconductor integrated circuit device includes a memory cell array, an error checking and correcting (ECC) circuit which performs an error checking and correcting operation for readout data read out from the normal data storing portion at data readout time during read latency and an I/O buffer. The memory cell array includes a normal data storing portion and a parity data storing portion. The normal data storing portion stores data for use in a normal data write and a normal data read. The parity data storing portion stores parity data for use in error checking and correcting. The EEC circuit carries out error checking and correcting read data read out from the normal data storing portion, during read latency cycle at a data read operation. The I/O buffer outputs the read data error checked and corrected by the ECC circuit, after the read latency cycle has lapsed.

Abstract: A semiconductor memory device is disclosed which comprises a cell array including a normal data section used for normal data write and read and a parity data section used for check data write and read, the check data being for execution of error check of data as read out of the normal data section, a data buffer for temporal stage of read data from the cell array and write data into the cell array, and an ECC circuit for generating the check data to be stored in the parity data section from write data as input during data writing, and for performing error check and correction of data read out of the normal section based on the data read out of the normal data section and the check data read out of said parity data section during data reading. N-bit parallel data transfer is performed between the data buffer and normal data section whereas m-bit parallel data transfer is done between the data buffer and external input/output terminals (where m and n are integers satisfying m<n).