Abstract: In an external memory interface circuit included in a signal processing circuit which is for processing an input signal by using an external memory, the external memory interface circuit carries out initialization of the external memory on reception of a clear signal. In the initialization, an end address detecting circuit detects an end address of an address signal generated by an address generator and produces an end address detection signal. A signal generating circuit continuously generates an enable signal, a write-in pulse signal, and an address increment pulse signal until the signal generating circuit receives the end address detection signal after reception of the clear signal. A reset signal generating circuit generates an address reset signal on reception of the enable signal. A write-in register successively produces zero data while the write-in register receives the enable signal to write the zero data in the external memory in synchronism with the write-in pulse signal.

Abstract: A static type random access memory device is equipped with sense amplifier circuits for rapidly developing small differential voltage levels respectively indicative of data bits read out from selected memory cells to digit line pairs, and the input nodes of each sense amplifier circuit are coupled with the associated digit line pair through a pair of capacitors, wherein the digit line pairs and the input nodes are respectively precharged to a high voltage level and an intermediate voltage level so that the sense amplifier circuits start on developing immediately after activation thereof.