Abstract: A tone signal generator includes a tone signal data generating device, a signal data generating device, and a sound effects imparting device, such as a digital signal processor. The sound effects are imparted to the tone signal data based on the signal data in such a way that the digital signal processor processes the tone signal data and the signal data by repeatedly multiplying and adding them. In the process, a signal data supplying device supplies the tone signal data to the signal data generating device so that the tone signal data is used in place of the signal data. The digital signal processor processes the first tone signal data generated by the tone signal generating device and the second tone signal device supplied by the signal data supplying device so that the sound effects are imparted to the first tone signal data based on the second tone signal data.

Abstract: A tone signal generator including a memory for storing tone signal data, a parameter generation device for generating parameter data, and a tone signal data generation device for generating the tone signal data by reading it from the memory, according to the parameter data. The generator includes also a level monitor device for monitoring a level of the tone signal data, and access control device to the memory. The access control device inhibits an access of the tone signal generation device to the memory when the level monitor device detects that the level of the tone signal data monitored is less than a specified value.Because the access control device inhibits the access of the tone signal generation device when the level of the tone signal data reaches the specified value, any other devices, such as a cpu, can access to the memory device in place of the tone signal generation device.

Abstract: A tone signal generator includes a plurality of tone generation channels, and a tone generation control data memory for storing instruction data for instructing tone generation or tone release and execution data for instructing execution thereof, for each tone generation channel. The tone signal generator also includes an execution device for executing the tone generation. The execution device executes the tone generation or the tone release for each tone generation channel at an assigned timing in the sampling cycle to the tone generation channel when the instruction data is written in the tone generation control data memory corresponding to the tone generation channel, and then the execution data is written in the memory corresponding to any tone generation channel. After the writing of the instruction data, the executing data is written into the memory. This executing data triggers the tone generation of channels where the instruction data has already been written.

Abstract: A tone generator has a waveform memory which stores waveform data at least having a loop section defined by a loop start address and a loop end address for repetitive reading out. An address-generating circuit generates a readout address by which the waveform data is read out from the waveform memory and delivers the readout address to the waveform memory to read out the waveform data from the waveform memory. A bit mask circuit masks a predetermined range of more significant bits of the readout address to generate a bit-masked address value. When it is determined that the readout address falls outside the loop section at least at one side of the loop start address and the loop end address of the loop section, a looping readout address generated by the use of the bit-masked address value is delivered as the readout address.

Abstract: A CRT controller is operated in accordance with a basic clock for a panel display and repeats a wait operation in response to a wait signal produced by a panel timing controller, which causes a compulsory synchronization with the panel timing. A 1/2 frame buffer is also provided. Display data supplied by the CRT controller and display data read from the 1/2 frame buffer are alternately selected such that data is supplied in an order conforming to the panel display of a double screen type panel display. A display of the double screen type panel display is controlled in accordance with an application program directed to a CRT display without modifying the order of the display data produced by the CRT controller and without changing the timing data which has been set in the CRT controller. The 1/2 frame buffer may be a general-purpose memory which stores 1/2 frame and one line of the panel display data.

Abstract: A CRT controller is operated in accordance with a basic clock for a panel display and repeats a wait operation in response to a wait signal produced by a panel timing controller, which causes a compulsory synchronization with the panel timing. A 1/2 frame buffer is also provided. Display data supplied by the CRT controller and display data read from the 1/2 frame buffer are alternately selected such that data is supplied in an order conforming to the panel display of a double screen type panel display. A display of the double screen type panel display is controlled in accordance with an application program directed to a CRT display without modifying the order of the display data produced by the CRT controller and without changing the timing data which has been set in the CRT controller. The 1/2 frame buffer may be a general-purpose memory which stores 1/2 frame and one line of the panel display data.