Abstract: An ATM cell switch has a cell multiplexer connected by a shared bus to a cell demultiplexer. In a first aspect of the invention, writing of cell data in the cell multiplexer is staggered to even out current consumption. In a second aspect, the cell multiplexer has input processors enabling it to receive cell data from input ports with different data rates, and the cell demultiplexer has output processors enabling it to send cell data to output ports with different data rates. In a third aspect, the multiplexing sequence on the shared bus is periodically altered to avoid favoring any one input port. In a fourth aspect, test pattern data are placed on the shared bus to monitor bus integrity. In a fifth aspect, the cell demultiplexer is divided into master and slave demultiplexer modules, which are coupled to different, parts of the shared bus.