Patents by Inventor Mitsuhiro Noguchi
Mitsuhiro Noguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088152Abstract: A semiconductor device of an embodiment includes N-wells and P-wells extending in a first direction and alternately arranged in a second direction orthogonal to the first direction; and a dummy gate formed above the N-wells and the P-wells so as to extend across at least one boundary between an N-well and a P-well that are adjacent to each other, the dummy gate being not connected to a wire, in which the dummy gate is formed in a region other than an end portion in the first direction of, among the N-wells and the P-wells, a well that has a width smaller than a predetermined threshold in the second direction.Type: ApplicationFiled: July 31, 2023Publication date: March 14, 2024Applicant: Kioxia CorporationInventors: Tomoaki SHINO, Mitsuhiro NOGUCHI, Takayuki TOBA
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Patent number: 11927561Abstract: The invention relates to a solid electrolyte comprised of partially stabilized zirconia, and a gas sensor including the solid electrolyte. The partially stabilized zirconia includes crystal particles, the crystal particles include at least stabilizer low-concentration phase particles, and the partially stabilized zirconia further includes voids. Among the stabilizer low-concentration phase particles, the presence rate of the stabilizer low-concentration phase particles where each distance from a void is 5 ?m or less is 65 volume percent or more. The stabilizer low-concentration phase particles include specific stabilizer low-concentration phase particles each having a distance of 5 ?m or less from an adjacent void in the voids, a presence rate of the specific stabilizer low-concentration phase particles having 65 volume percent or more.Type: GrantFiled: May 1, 2020Date of Patent: March 12, 2024Assignee: DENSO CORPORATIONInventors: Makoto Noguchi, Satoshi Suzuki, Mitsuhiro Yoshida
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Patent number: 11756898Abstract: A semiconductor memory device includes: two memory blocks; a first structure disposed between the two memory blocks; and a second structure separated from the two memory blocks, or a plurality of second structures. The two memory blocks include a plurality of first conductive layers and a plurality of first insulating layers alternately arranged. The first structure has one end, and the one end is closer to the substrate than the plurality of first conductive layers are. The second structure has one end, and the one end is closer to the substrate than at least apart of the first conductive layers among the plurality of first conductive layers is. Another end of the first structure and another end of the second structure are farther from the substrate than the plurality of first conductive layers are. The second structure is separated from the first structure.Type: GrantFiled: December 14, 2020Date of Patent: September 12, 2023Assignee: KIOXIA CORPORATIONInventors: Hideki Itai, Mitsuhiro Noguchi, Hiromasa Yoshimori, Hideyuki Tabata, Yasushi Nakajima
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Patent number: 11574994Abstract: A semiconductor device according to embodiments includes: a first conductivity-type first semiconductor layer set to a first potential; a second conductivity-type second semiconductor layer stacked on the first semiconductor layer and set to a second potential; an interlayer insulating film disposed on a main surface of the second semiconductor layer; a resistor disposed above the first semiconductor layer while interposing the second semiconductor layer and the interlayer insulating film therebetween; and a terminal electrically connected to the second semiconductor layer.Type: GrantFiled: March 24, 2021Date of Patent: February 7, 2023Assignee: Kioxia CorporationInventors: Masahiro Shimura, Mitsuhiro Noguchi
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Patent number: 11462556Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.Type: GrantFiled: October 15, 2020Date of Patent: October 4, 2022Assignee: Kioxia CorporationInventors: Tetsuya Furukawa, Tomoaki Shino, Mitsuhiro Noguchi, Shinichi Watanabe, Yukio Nishida, Hiroyasu Tanaka
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Publication number: 20220271050Abstract: A semiconductor device for controlling memory cell transistors includes a substrate, a first well of a first conductivity type in the substrate, a second well of a second conductivity type that electrically separates the first well from the substrate therein and includes a first portion surrounding the first well, and a second portion facing a bottom portion of the first well and having a side surface contacting a side surface of the first portion, a third well of the first conductivity type in the substrate, the third well surrounding the first portion of the second well with being separated therefrom, and a first transistor that includes a gate electrode facing the first well via a first insulating film. A bottom surface of the first portion of the second well is closer to a surface of the substrate than a bottom surface of the second portion of the second well.Type: ApplicationFiled: August 27, 2021Publication date: August 25, 2022Inventors: Mitsuhiro NOGUCHI, Masahiro SHIMURA
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Patent number: 11251122Abstract: A semiconductor device includes: wiring layers laminated in a first direction and including conducting members; and a second wiring layer including a bonding pad electrode. The first wiring layers each include a bonding pad area. The bonding pad area overlaps with the bonding pad electrode viewed in the first direction. The conducting member is absent in an area inside a first imaginary circle with a first point as a midpoint in the bonding pad area. The conducting members are disposed in an area outside a second imaginary circle in the bonding pad area. The second imaginary circle has the first point as a midpoint and has a radius equal to or more than a radius of the first imaginary circle. When the radius of the first imaginary circle is denoted as R1 and the radius of the second imaginary circle is denoted as R2, R2/R1 is smaller than 1/cos(?/4).Type: GrantFiled: August 4, 2020Date of Patent: February 15, 2022Assignee: Kioxia CorporationInventors: Masayuki Akou, Mitsuhiro Noguchi, Yuuichi Tatsumi
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Patent number: 11239317Abstract: According to a certain embodiment, the nonvolatile semiconductor memory device includes: a first conductivity-type semiconductor substrate including a crushed layer on a back side surface thereof; a memory cell array disposed on a front side surface of the semiconductor substrate opposite to the crushed layer; and a first conductivity-type high voltage transistor HVP disposed on the semiconductor substrate and including a first conductivity-type channel, configured to supply a high voltage to the memory cell array. The first conductivity-type high voltage transistor includes: a well region NW disposed on the surface of the semiconductor substrate and having a second conductivity type; a source region and a drain region disposed in the well region; and a first conductivity-type first high concentration layer WT2 disposed between the crushed layer of the semiconductor substrate and the well region and having a higher concentration than an impurity concentration of the semiconductor substrate.Type: GrantFiled: March 3, 2020Date of Patent: February 1, 2022Assignee: Kioxia CorporationInventors: Shoichi Watanabe, Mitsuhiro Noguchi
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Patent number: 11227915Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer on a semiconductor substrate and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer is between the second semiconductor layer and the semiconductor substrate in a first direction. A first conductive layer is on the second semiconductor layer and contacting the second semiconductor layer. A third semiconductor layer is spaced from the second semiconductor layer in a second direction and connected to the first semiconductor layer. A second conductive layer is spaced from the first conductive layer in the second direction and connected to the third semiconductor layer. Each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer extends lengthwise in a third direction intersecting the first direction and the second direction.Type: GrantFiled: August 18, 2020Date of Patent: January 18, 2022Assignee: KIOXIA CORPORATIONInventors: Ryuta Tezuka, Mitsuhiro Noguchi, Tomoaki Shino
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Publication number: 20220005767Abstract: A semiconductor memory device includes: two memory blocks; a first structure disposed between the two memory blocks; and a second structure separated from the two memory blocks, or a plurality of second structures. The two memory blocks include a plurality of first conductive layers and a plurality of first insulating layers alternately arranged. The first structure has one end, and the one end is closer to the substrate than the plurality of first conductive layers are. The second structure has one end, and the one end is closer to the substrate than at least apart of the first conductive layers among the plurality of first conductive layers is. Another end of the first structure and another end of the second structure are farther from the substrate than the plurality of first conductive layers are. The second structure is separated from the first structure.Type: ApplicationFiled: December 14, 2020Publication date: January 6, 2022Applicant: KIOXIA CORPORATIONInventors: Hideki ITAI, Mitsuhiro NOGUCHI, Hiromasa YOSHIMORI, Hideyuki TABATA, Yasushi NAKAJIMA
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Publication number: 20210305368Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer on a semiconductor substrate and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer is between the second semiconductor layer and the semiconductor substrate in a first direction. A first conductive layer is on the second semiconductor layer and contacting the second semiconductor layer. A third semiconductor layer is spaced from the second semiconductor layer in a second direction and connected to the first semiconductor layer. A second conductive layer is spaced from the first conductive layer in the second direction and connected to the third semiconductor layer. Each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer extends lengthwise in a third direction intersecting the first direction and the second direction.Type: ApplicationFiled: August 18, 2020Publication date: September 30, 2021Inventors: Ryuta TEZUKA, Mitsuhiro NOGUCHI, Tomoaki SHINO
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Publication number: 20210210592Abstract: A semiconductor device according to embodiments includes: a first conductivity-type first semiconductor layer set to a first potential; a second conductivity-type second semiconductor layer stacked on the first semiconductor layer and set to a second potential; an interlayer insulating film disposed on a main surface of the second semiconductor layer; a resistor disposed above the first semiconductor layer while interposing the second semiconductor layer and the interlayer insulating film therebetween; and a terminal electrically connected to the second semiconductor layer.Type: ApplicationFiled: March 24, 2021Publication date: July 8, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Masahiro SHIMURA, Mitsuhiro NOGUCHI
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Publication number: 20210134713Abstract: A semiconductor device includes: wiring layers laminated in a first direction and including conducting members; and a second wiring layer including a bonding pad electrode. The first wiring layers each include a bonding pad area. The bonding pad area overlaps with the bonding pad electrode viewed in the first direction. The conducting member is absent in an area inside a first imaginary circle with a first point as a midpoint in the bonding pad area. The conducting members are disposed in an area outside a second imaginary circle in the bonding pad area. The second imaginary circle has the first point as a midpoint and has a radius equal to or more than a radius of the first imaginary circle. When the radius of the first imaginary circle is denoted as R1 and the radius of the second imaginary circle is denoted as R2, R2/R1 is smaller than 1/cos(?/4).Type: ApplicationFiled: August 4, 2020Publication date: May 6, 2021Applicant: Kioxia CorporationInventors: Masayuki AKOU, Mitsuhiro NOGUCHI, Yuuichi TATSUMI
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Patent number: 10985237Abstract: A semiconductor device according to embodiments includes: a first conductivity-type first semiconductor layer set to a first potential; a second conductivity-type second semiconductor layer stacked on the first semiconductor layer and set to a second potential; an interlayer insulating film disposed on a main surface of the second semiconductor layer; a resistor disposed above the first semiconductor layer while interposing the second semiconductor layer and the interlayer insulating film therebetween; and a terminal electrically connected to the second semiconductor layer.Type: GrantFiled: September 9, 2019Date of Patent: April 20, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masahiro Shimura, Mitsuhiro Noguchi
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Publication number: 20210074811Abstract: According to a certain embodiment, the nonvolatile semiconductor memory device includes: a first conductivity-type semiconductor substrate including a crushed layer on a back side surface thereof; a memory cell array disposed on a front side surface of the semiconductor substrate opposite to the crushed layer; and a first conductivity-type high voltage transistor HVP disposed on the semiconductor substrate and including a first conductivity-type channel, configured to supply a high voltage to the memory cell array. The first conductivity-type high voltage transistor includes: a well region NW disposed on the surface of the semiconductor substrate and having a second conductivity type; a source region and a drain region disposed in the well region; and a first conductivity-type first high concentration layer WT2 disposed between the crushed layer of the semiconductor substrate and the well region and having a higher concentration than an impurity concentration of the semiconductor substrate.Type: ApplicationFiled: March 3, 2020Publication date: March 11, 2021Applicant: Kioxia CorporationInventors: Shoichi WATANABE, Mitsuhiro NOGUCHI
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Publication number: 20210028185Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.Type: ApplicationFiled: October 15, 2020Publication date: January 28, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tetsuya FURUKAWA, Tomoaki SHINO, Mitsuhiro NOGUCHI, Shinichi WATANABE, Yukio NISHIDA, Hiroyasu TANAKA
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Patent number: 10840257Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.Type: GrantFiled: February 11, 2019Date of Patent: November 17, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Tetsuya Furukawa, Tomoaki Shino, Mitsuhiro Noguchi, Shinichi Watanabe, Yukio Nishida, Hiroyasu Tanaka
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Publication number: 20200295125Abstract: A semiconductor device according to embodiments includes: a first conductivity-type first semiconductor layer set to a first potential; a second conductivity-type second semiconductor layer stacked on the first semiconductor layer and set to a second potential; an interlayer insulating film disposed on a main surface of the second semiconductor layer; and a resistor disposed above the first semiconductor layer while interposing the second semiconductor layer and the interlayer insulating film therebetween; and a terminal electrically connected to the second semiconductor layer.Type: ApplicationFiled: September 9, 2019Publication date: September 17, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Masahiro SHIMURA, Mitsuhiro NOGUCHI
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Publication number: 20200066743Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.Type: ApplicationFiled: February 11, 2019Publication date: February 27, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tetsuya FURUKAWA, Tomoaki SHINO, Mitsuhiro NOGUCHI, Shinichi WATANABE, Yukio NISHIDA, Hiroyasu TANAKA
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Patent number: RE49274Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.Type: GrantFiled: February 25, 2019Date of Patent: November 1, 2022Assignee: KIOXIA CORPORATIONInventors: Dai Nakamura, Hiroyuki Kutsukake, Kenji Gomikawa, Takeshi Shimane, Mitsuhiro Noguchi, Koji Hosono, Masaru Koyanagi, Takashi Aoi