Patents by Inventor Mitsuhiro Okune

Mitsuhiro Okune has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10475704
    Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into element chips 10 by exposing the substrate to a first plasma. Therefore, element chips having a first surface, a second surface, and a side surface connecting the first surface and the second surface are held spaced from each other on a carrier. A protection film covering the element chip is formed only on the side surface and it is possible to suppress creep-up of a conductive material to the side surface in the mounting step by exposing the element chips to second plasma in which a mixed gas of fluorocarbon and helium is used as a raw material gas.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: November 12, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara, Mitsuru Hiroshima, Mitsuhiro Okune
  • Patent number: 9922899
    Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into the element chips by exposing the substrate to first plasma. Therefore, the element chips having a first surface, a second surface, and a side surface on which a plurality of convex portions are formed are held spaced from each other on a carrier. A protection film is formed on the side surface of the element chip by exposing the element chip to second plasma, at least convex portions formed on the side surface are covered by the protection film in the protection film formation, and creep-up of a conductive material to the side surface is suppressed in the mounting step.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: March 20, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara, Mitsuru Hiroshima, Mitsuhiro Okune
  • Publication number: 20170229365
    Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into element chips 10 by exposing the substrate to a first plasma. Therefore, element chips having a first surface, a second surface, and a side surface connecting the first surface and the second surface are held spaced from each other on a carrier. A protection film covering the element chip is formed only on the side surface and it is possible to suppress creep-up of a conductive material to the side surface in the mounting step by exposing the element chips to second plasma in which a mixed gas of fluorocarbon and helium is used as a raw material gas.
    Type: Application
    Filed: January 18, 2017
    Publication date: August 10, 2017
    Inventors: ATSUSHI HARIKAI, SHOGO OKITA, NORIYUKI MATSUBARA, MITSURU HIROSHIMA, MITSUHIRO OKUNE
  • Publication number: 20170229366
    Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into the element chips by exposing the substrate to first plasma. Therefore, the element chips having a first surface, a second surface, and a side surface on which a plurality of convex portions are formed are held spaced from each other on a carrier. A protection film is formed on the side surface of the element chip by exposing the element chip to second plasma, at least convex portions formed on the side surface are covered by the protection film in the protection film formation, and creep-up of a conductive material to the side surface is suppressed in the mounting step.
    Type: Application
    Filed: January 18, 2017
    Publication date: August 10, 2017
    Inventors: ATSUSHI HARIKAI, SHOGO OKITA, NORIYUKI MATSUBARA, MITSURU HIROSHIMA, MITSUHIRO OKUNE
  • Patent number: 9698073
    Abstract: In a plasma processing step in a method of manufacturing an element chip in which a plurality of element chips are manufactured by dividing a substrate, which has a plurality of element regions, the substrate is divided into element chips by exposing the substrate to first plasma. In a protection film forming step of forming a protection film covering a side surface and a second surface by exposing the element chips to second plasma of which raw material gas is mixed gas of carbon fluoride and helium, protection film forming conditions are set such that a thickness of a second protection film of the second surface is greater than a thickness of a first protection film of the side surface.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: July 4, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara, Mitsuru Hiroshima, Mitsuhiro Okune
  • Publication number: 20170098591
    Abstract: In a plasma processing step in a method of manufacturing an element chip in which a plurality of element chips are manufactured by dividing a substrate, which has a plurality of element regions, the substrate is divided into element chips by exposing the substrate to first plasma. In a protection film forming step of forming a protection film covering a side surface and a second surface by exposing the element chips to second plasma of which raw material gas is mixed gas of carbon fluoride and helium, protection film forming conditions are set such that a thickness of a second protection film of the second surface is greater than a thickness of a first protection film of the side surface.
    Type: Application
    Filed: September 14, 2016
    Publication date: April 6, 2017
    Inventors: ATSUSHI HARIKAI, SHOGO OKITA, NORIYUKI MATSUBARA, MITSURU HIROSHIMA, MITSUHIRO OKUNE
  • Publication number: 20150059980
    Abstract: In plasma processing, damage on a cover is prevented while thermal effect on an annular frame is suppressed. Plasma processing is applied to a substrate held by a carrier including an annular frame and a holding sheet. There are provided a chamber having a decompressible internal space, a plasma source for generating plasma in the chamber, a stage that is provided in the chamber and places the carrier thereon, and a cover that is placed above the stage to cover the holding sheet and the frame, and has a window penetrating through the thickness of the cover. The cover is made of a material having a high thermal conductivity, and a front face exposed to plasma, at least on the side of the window of the cover, is covered with a protect part made of a material having a low reactivity with plasma.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 5, 2015
    Inventors: Shogo OKITA, Mitsuhiro OKUNE
  • Patent number: 8673166
    Abstract: In a plasma processing apparatus, thrust-up pins are elevated and a thrust-up force is detected when electrostatic attraction for a substrate by a substrate holding device is ceased after completion of plasma processing, the elevation of the thrust-up pins is ceased upon detection of a detection threshold, and a stepped elevating operation in which the elevation and stoppage of the thrust-up pins are repeated a plurality of times are thereafter commenced on condition that the detected thrust-up force falls to or below the detection threshold and that release of the substrate from a placement surface has not been completed. In the stepped elevating operation, operation timing of the thrust-up device is controlled so that the completion of the release of the substrate from the placement surface is detected when the thrust-up pins are stopped after being elevated and so that the stepped elevating operation is continued on condition that the release has not been completed.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: March 18, 2014
    Assignee: Panasonic Corporation
    Inventors: Shogo Okita, Hiromi Asakura, Syouzou Watanabe, Toshihiro Wada, Mitsuhiro Okune, Mitsuru Hiroshima
  • Publication number: 20120094500
    Abstract: An object of the present invention is suppressing notches in dry etching of a processing object where an etched layer made of a silicon material is formed on an etching stop layer. A substrate has an etched layer made of a silicon material on an etching stop layer. SF6/C4F8 gas, as an etching gas, is supplied to generate plasma, and a portion of the etched layer exposed through a resist mask is etched. A sidewall protection layer made of polymer is formed on a sidewall of a trench or a hole.
    Type: Application
    Filed: December 23, 2011
    Publication date: April 19, 2012
    Inventors: Mitsuhiro Okune, Hiroyuki Suzuki
  • Publication number: 20110111601
    Abstract: In a plasma processing apparatus, thrust-up pins are elevated and a thrust-up force is detected when electrostatic attraction for a substrate by a substrate holding device is ceased after completion of plasma processing, the elevation of the thrust-up pins is ceased upon detection of a detection threshold, and a stepped elevating operation in which the elevation and stoppage of the thrust-up pins are repeated a plurality of times are thereafter commenced on condition that the detected thrust-up force falls to or below the detection threshold and that release of the substrate from a placement surface has not been completed. In the stepped elevating operation, operation timing of the thrust-up device is controlled so that the completion of the release of the substrate from the placement surface is detected when the thrust-up pins are stopped after being elevated and so that the stepped elevating operation is continued on condition that the release has not been completed.
    Type: Application
    Filed: May 28, 2009
    Publication date: May 12, 2011
    Inventors: Shogo Okita, Hiromi Asakura, Syouzou Watanabe, Toshihiro Wada, Mitsuhiro Okune, Mitsuru Hiroshima
  • Publication number: 20090218045
    Abstract: The plasma processing apparatus has a beam-shaped spacer 7 placed at the upper opening of the chamber 3 opposed to the substrate 2. The beam-shaped spacer 7 has an annular outer peripheral portion 7a whose lower surface 7d is supported by the chamber 3, a central portion 7b located at the center of a region surrounded by the outer peripheral portion 7a in plane view, and a plurality of beam portions 7c extending radially from the central portion 7b to the outer peripheral portion 7a. An entire of a dielectric plate 8 is uniformly supported by the beam-shaped spacer 7. The dielectric plate 8 can be reduces in thickness while securing a mechanical strength for supporting the atmospheric pressure when the chamber 3 is internally reduced in pressure.
    Type: Application
    Filed: November 1, 2006
    Publication date: September 3, 2009
    Inventors: Mitsuru Hiroshima, Hiromi Asakura, Syouzou Watanabe, Mitsuhiro Okune, Hiroyuki Suzuki, Ryuzou Houchin
  • Publication number: 20080138993
    Abstract: A dry etching apparatus comprises: a vacuum chamber where a processing target is disposed on a bottom wall side of an internal space; a coil for generating plasma that is disposed above and outside the vacuum chamber and has conductors disposed so that a gap is formed in a plane view; a top wall that closes the top of the internal space and has a transparent section at a position corresponding to the gap between conductors of the coil 36 in the plane view; and a camera that is disposed above the coil and can capture at least a part of the processing target in a field of view through the gap and the transparent section. The status of the processing target during plasma processing can be observed in real-time.
    Type: Application
    Filed: December 6, 2005
    Publication date: June 12, 2008
    Inventors: Mitsuru Hiroshima, Sumio Miyake, Mitsuhiro Okune, Shozoh Watanabe, Hiroyuki Suzuki
  • Publication number: 20080093338
    Abstract: An object of the present invention is suppressing notches in dry etching of a processing object where an etched layer made of a silicon material is formed on an etching stop layer. A substrate 12 has an etched layer 22 made of a silicon material on an etching stop layer 21. SF6/C4F8 gas, as an etching gas, is supplied to generate plasma, and a portion of the etched layer exposed through a resist mask 23 is etched. A sidewall protection layer 24 made of polymer is formed on a sidewall of a trench or hole.
    Type: Application
    Filed: December 6, 2005
    Publication date: April 24, 2008
    Inventors: Mitsuhiro Okune, Hiroyuki Suzuki
  • Publication number: 20070131652
    Abstract: An object of the present invention is to provide a plasma etching method by which both of a requirement for a trench shape and a requirement for a aspect ratio can be satisfied, and a trench having a side wall of a smooth shape can be formed. According to the present invention, a silicon substrate is placed on a lower electrode (120), etching gas is supplied through a gas introducing port (140) and exhausted from an exhaust port (150), high frequency powers (130a, 130b) supply high-frequency electricity to an upper electrode (110) and a lower electrode (120), respectively, in order to energize the etching gas into plasma state, using an ICP method, and then activated species are generated to make etching of the silicon substrate be progressed. As the etching gas, mixed gas, which includes mainly SF6 gas added with O2 gas and He gas, is used.
    Type: Application
    Filed: November 26, 2004
    Publication date: June 14, 2007
    Inventors: Mitsuhiro Okune, Mitsuru Hiroshima, Hiroyuki Suzuki, Sumio Miyake, Shouzou Watanabe