Patents by Inventor Mitsuhiro Saeki

Mitsuhiro Saeki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7868892
    Abstract: An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: January 11, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hirotaka Hara, Hiroyuki Hamasaki, Mitsuhiro Saeki, Kazuhiro Hirade, Makoto Takano
  • Publication number: 20090015590
    Abstract: An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.
    Type: Application
    Filed: September 24, 2008
    Publication date: January 15, 2009
    Inventors: HIROTAKA HARA, Hiroyuki Hamasaki, Mitsuhiro Saeki, Kazuhiro Hirade, Makoto Takano
  • Patent number: 7446775
    Abstract: An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: November 4, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Hirotaka Hara, Hiroyuki Hamasaki, Mitsuhiro Saeki, Kazuhiro Hirade, Makoto Takano
  • Publication number: 20050030311
    Abstract: An object of the present invention is to improve efficiency of transfer of control information, graphic data, and the like for drawing and display control in a graphic data processor. A graphic data processor includes: a CPU; a first bus coupled to the CPU; a DMAC for controlling a data transfer using the first bus; a bus bridge circuit for transmitting/receiving data to/from the first bus; a three-dimensional graphics module for receiving a command from the CPU via the first bus and performing a three-dimensional graphic process; a second bus coupled to the bus bridge circuit and a plurality of first circuit modules; a third bus coupled to the bus bridge circuit and second circuit modules; and a memory interface circuit coupled to the first and second buses and the three-dimensional graphic module and connectable to an external memory, wherein the bus bridge circuit can control a direct memory access transfer between an external circuit and the second bus.
    Type: Application
    Filed: July 15, 2004
    Publication date: February 10, 2005
    Inventors: Hirotaka Hara, Hiroyuki Hamasaki, Mitsuhiro Saeki, Kazuhiro Hirade, Makoto Takano