Patents by Inventor Mitsuhiro Saitou
Mitsuhiro Saitou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20020020910Abstract: Several electronic parts are mounted on several ceramic substrates in a semiconductor device, and are wire bonded to the respective ceramic substrates through bonding wires. The electronic parts and the bonding wires are covered with an enclosing member on every ceramic substrate, and an inside of the enclosing member is filled with silicone gel for sealing. The ceramic substrates are bonded to a radiation fin together, and are mounted on a motherboard perpendicularly to the motherboard.Type: ApplicationFiled: August 1, 2001Publication date: February 21, 2002Inventors: Kan Kinouchi, Mitsuhiro Saitou, Takashi Nagasaka, Yuji Ootani, Hiroyuki Yamakawa, Koji Takeuchi, Hirokazu Imai, Yukihiro Maeda, Atsushi Kanamori
-
Publication number: 20020017697Abstract: A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.Type: ApplicationFiled: September 5, 2001Publication date: February 14, 2002Applicant: Denso CorporationInventors: Yasuhiro Kitamura, Toshio Sakakibara, Kenji Kohno, Shoji Mizuno, Yoshiaki Nakayama, Hiroshi Maeda, Makio Iida, Hiroshi Fujimoto, Mitsuhiro Saitou, Hiroshi Imai, Hiroyuki Ban
-
Patent number: 6242787Abstract: A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.Type: GrantFiled: November 15, 1996Date of Patent: June 5, 2001Assignee: Denso CorporationInventors: Yoshiaki Nakayama, Hiroshi Maeda, Makio Iida, Hiroshi Fujimoto, Mitsuhiro Saitou, Hiroshi Imai, Hiroyuki Ban
-
Patent number: 6157246Abstract: The present invention is aimed at avoiding noise generation accompanying switching actions in booster circuits for a load such as an air-bag driving circuit. In an air-bag driving circuit, which is designed to actuate an igniting transistor 13 in response to output of a collision detecting signal from a collision detector 7 for detecting a collision condition of a vehicle so as to supply an igniting current to a squib 11 based on a voltage boosted by booster circuits 4 and 5, the boosting operation of the booster circuits 4 and 5 is inhibited while the collision detecting signal is absent and started when the collision detecting signal is output from the collision detector 7.Type: GrantFiled: July 2, 1998Date of Patent: December 5, 2000Assignee: Denso CorporationInventors: Mitsuhiro Saitou, Hiroyuki Ban
-
Patent number: 6104078Abstract: A semiconductor device including a semiconductor substrate having a main surface. An insulating film is formed on the main surface of the semiconductor substrate. A semiconductor layer is placed on the insulating film. Side insulating regions extending from a surface of the semiconductor layer to the insulating film divide the semiconductor layer into element regions. The element regions are isolated from each other by the side insulating regions and the insulating film. The semiconductor substrate has a resistivity of 1.5 .OMEGA.cm or lower. A voltage at the semiconductor substrate is set to a given voltage.Type: GrantFiled: September 30, 1997Date of Patent: August 15, 2000Assignee: DENSO CorporationInventors: Makio Iida, Mitsuhiro Saitou, Akitaka Murata, Hiroyuki Ban, Tadashi Suzuki, Toshio Sakakibara, Takayuki Sugisaka, Shoji Miura
-
Patent number: 6104076Abstract: A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.Type: GrantFiled: November 15, 1996Date of Patent: August 15, 2000Assignee: Denso CorporationInventors: Yoshiaki Nakayama, Hiroshi Maeda, Makio Iida, Hiroshi Fujimoto, Mitsuhiro Saitou, Hiroshi Imai, Hiroyuki Ban
-
Patent number: 6081040Abstract: An alignment mark for determining a position of a thin film resistor formed on a semiconductor chip. The alignment mark is disposed on a capacitor formation region of the semiconductor chip. Because aluminum wiring members of the semiconductor chip are not disposed adjacent to the alignment mark within the capacitor formation region, the alignment mark can be precisely recognized. As a result, the position of the thin film resistor can be also precisely determined.Type: GrantFiled: March 16, 1998Date of Patent: June 27, 2000Assignee: Denso CorporationInventors: Shoichi Okuda, Mitsuhiro Saitou, Hiroyuki Ban
-
Patent number: 6034556Abstract: An operational amplifier charges a charge storage capacitor in response to an input signal supplied to a non-inverting input terminal. When a switching signal is low, NPN transistors disposed in an output open circuit are on. Therefore, output transistors disposed in a push-pull circuit are off and the output signal is cut off. Further, in this situation, the potential of a phase compensation capacitor is held because AC coupling of the phase compensation capacitor does not occur.Type: GrantFiled: February 5, 1998Date of Patent: March 7, 2000Assignee: Denso CorporationInventors: Takahisa Koyasu, Mitsuhiro Saitou, Hiroyuki Ban
-
Patent number: 5982604Abstract: A power supply apparatus is provided for energizing an electronic control unit mounted on a vehicle having a battery and a starter switch. The apparatus includes a coil connected to the power supply line, and a switch which operates for selectively enabling a current to flow through the coil and cutting off the current through the coil. A control circuit operates for selectively changing the switch between an ON state and an OFF state when the starter switch assumes an ON position. The ON and OFF states alternate in accordance with predetermined delays.Type: GrantFiled: March 19, 1998Date of Patent: November 9, 1999Assignee: Denso CorporationInventors: Akio Kojima, Mitsuhiro Saitou, Kiyoshi Yamamoto
-
Patent number: 5977651Abstract: A drive circuit for a vehicle occupant safety apparatus includes a device for activating the vehicle occupant safety apparatus. A first transistor is connected in series with the device. A constant-current circuit receives electric energy from a power supply, and feeds a constant current to the device when the first transistor falls into its on state. The constant-current circuit includes a second transistor connected in series with the device. The second transistor includes an N-channel field-effect transistor. A third transistor is connected to the second transistor. The second and third transistors form a current mirror circuit. The third transistor includes an N-channel field-effect transistor. A voltage between a gate and a source of the third transistor is regulated at a constant level. Gate voltages of the second and third transistors are controlled in response to source voltages of the second and third transistors to equalize the source voltages of the second and third transistors.Type: GrantFiled: October 31, 1997Date of Patent: November 2, 1999Assignee: Denso CorporationInventors: Nobumasa Ueda, Nobuo Mayumi, Mitsuhiro Saitou, Shoichi Okuda
-
Patent number: 5917246Abstract: A semiconductor package, which secures the protection of circuit elements from the external environment, is disclosed. A single in-line package (SIP) is constructed by fixingly sealing a hybrid integrated circuit component within a casing with epoxy resin. A sleeve is bonded on the surface of a ceramic substrate. The sleeve is formed with silicon rubber into a pocket shape so as to cover respective circuit elements of the hybrid integrated circuit component. In the sleeve is made an opening part. Silicon gel is poured into the sleeve as a fixingly sealing material and cured to seal the respective circuit elements. Terminals downwardly extends in parallel with each other from an end part of the ceramic substrate through an opening part of the casing.Type: GrantFiled: March 22, 1996Date of Patent: June 29, 1999Assignee: Nippondenso Co., Ltd.Inventors: Hirokazu Kasuya, Kouji Numazaki, Takahisa Koyasu, Mitsuhiro Saitou
-
Patent number: 5739546Abstract: A semiconductor wafer, having a relatively wide power supply line and ground line, and which can also prevent short-circuiting between these lines. Multiple integrated circuit formation regions, whereon integrated circuits have been formed, are disposed on a semiconductor wafer. A silicon oxide film is formed on a silicon substrate, and a ground line conductor is formed on the silicon oxide film. This ground line conductor is extended over scribe lines. A layer insulation film composed of silicon oxide film is deposited on the silicon oxide film with the ground line conductor interposed therebetween, and a power supply line conductor is formed on the layer insulation film to overlap the ground line conductor. The power supply line conductor is extended over scribe lines. In the integrated circuit formation regions, a power supply pad and the power supply line conductor are electrically connected. A ground pad and the ground line conductor are also electrically connected.Type: GrantFiled: June 18, 1996Date of Patent: April 14, 1998Assignee: Nippondenso Co., Ltd.Inventors: Mitsuhiro Saitou, Kouji Numazaki, Hiroyuki Ban
-
Patent number: 5719522Abstract: A variable load current supply unit supplies a current to be consumed by a constant voltage output unit to a power source terminal thereof, and supplies a current to be consumed by a load circuit thereto through a reference voltage output terminal. The constant voltage output unit maintains a potential of the power source terminal thereof, i.e., a potential of the reference voltage output terminal, at a fixed potential. A base potential control unit negatively feeds back changes in the potential on the reference voltage output terminal to a base of an emitter follower transistor in the variable load current supply unit. In this way, when the current consumed by the load current is reduced and the potential on the reference voltage output terminal thereby slightly increases the current supplied by the variable load current supply unit decreases.Type: GrantFiled: March 12, 1997Date of Patent: February 17, 1998Assignee: Nippondenso Co., Ltd.Inventors: Mitsuhiro Saitou, Hajime Ito, Kiyoshi Yamamoto, Hiroyuki Ban
-
Patent number: 5629702Abstract: An analog to digital converter comprises: first to n.sup.th comparators, having a tandem structure, for comparing an input voltage signal with first to n.sup.th reference voltages and outputting first to n.sup.th bit outputs respectively, said n being a natural number more than one, said first comparator outputting a most significant bit of said first bit output; a first reference voltage generation circuit for generating said first reference voltage; second to n.sup.th reference voltage generation circuits for generating said second to n.sup.th reference voltages, p.sup.th reference voltages being generated in accordance with outputs of said first to (p-1).sup.th comparators, said p being a natural number and l<p<n.Type: GrantFiled: October 5, 1994Date of Patent: May 13, 1997Assignee: Nippondenso Co., Ltd.Inventors: Takahisa Koyasu, Mitsuhiro Saitou
-
Patent number: 5593722Abstract: A method is provided for easily producing thick multi-layer substrates maintaining highly accurate resistances with little variation. A thick-film resistor 6 on a ceramic substrate 1 is fired at a temperature higher than the temperature of firing a glass insulating layer 2 that is formed thereon in contact therewith. This makes it possible to decrease the change in the resistance in a subsequent high-temperature step of firing the glass insulating layers 2 to 4. Moreover, after the glass insulating layer 2 is formed on the thick-film resistor 6 on the ceramic substrate 1, laser trimming is effected through a window or the glass insulating layer 2 and, thereafter, the glass insulating layers 3 and 4 are formed. This makes it possible to decrease the change in the resistance of the thick-film resistor 6 after laser trimming and to reduce the laser output.Type: GrantFiled: February 9, 1996Date of Patent: January 14, 1997Assignee: Nippondenso Co., Ltd.Inventors: Yuji Otani, Takashi Nagasaka, Mitsuhiro Saitou
-
Patent number: 5562973Abstract: In a ceramic multi-layer wiring board, a surface conductor layer is made of a copper-based material and an inner conductor in the ceramic multi-layer is a non-copper metal having a melting point higher than a temperature at which the ceramic multi-layer is fired, typically Ag. Cu and Ag form eutectic crystals when firing the surface conductor layer of Cu. This can be prevented by connecting the surface conductor layer and the inner conductor with Ag--Pd or a metal which is different from the materials of the surface wiring layer and the inner conductor and which does not form eutectic crystals with the material of the surface wiring layer at the temperature at which the surface wiring layer is fired.Type: GrantFiled: June 6, 1995Date of Patent: October 8, 1996Assignee: Nippondenso Co. Ltd.Inventors: Takashi Nagasaka, Yuji Otani, Mitsuhiro Saitou
-
Patent number: 5554881Abstract: At least four electrodes are provided on the same surface of a discrete transistor. Among these electrodes, one electrode is set as a base electrode, an electrode neighboring the base electrode in the up-and-down direction is set as an emitter electrode and an electrode neighboring the base electrode in the right-and-left direction is set as a collector electrode. On the same surface, a base electrode is provided at a position which is neither in the up-and-down direction nor in the right-and-left direction with respect to the base electrode. When the discrete transistor having this type of electrode arrangement is mounted on a substrate, one of the base electrodes formed on the substrate is connected to a first wiring, the collector electrode is connected to a second wiring, and the emitter electrode is connected to a third wiring.Type: GrantFiled: December 15, 1994Date of Patent: September 10, 1996Assignee: Nippondenso Co., Ltd.Inventors: Takahisa Koyasu, Kouji Numazaki, Hirokazu Kasuya, Mitsuhiro Saitou, Kazuhisa Ikeda
-
Patent number: 5554947Abstract: A wave-shaping circuit is provided which converts an input alternating signal into a pulse signal. The wave-shaping circuit includes a level-adjusting circuit which is designed to integrate the input alternating signal to determine a central level of amplitude thereof for adjusting the central level to a given reference level under feedback control. This compensates for the variation in central level of amplitude of the input alternating signal caused by various noise components contained therein.Type: GrantFiled: October 7, 1994Date of Patent: September 10, 1996Assignee: Nippondenso Co., Ltd.Inventors: Mitsuhiro Saitou, Hideki Kabune
-
Patent number: 5483217Abstract: An electronic circuit device decreases dispersion in the output of the circuit caused by changes in the resistance of the resistors resulting from stress. Resistor positions are selected on the circuit board so that a change in the circuit output caused by a change in resistance of a first resistor group becomes equal to a change caused by a change in resistance caused by a second resistor group, these changes being in opposite directions so as to cancel each other. Alternately, a plurality of resistors are connected to form a composite resistor such that the effect upon resistance of the composite resistor caused by the resistor having decreased resistance is cancelled by the effect upon resistance of the composite resistor caused by a resistor having an increased resistance.Type: GrantFiled: July 15, 1993Date of Patent: January 9, 1996Assignee: Nippondenso Co., Ltd.Inventors: Takashi Nagasaka, Mitsuhiro Saitou, Takahisa Koyasu, Hiroyuki Ban, Yuji Otani, Kengo Oka, Kyoko Nagaoka
-
Patent number: 5439732Abstract: In a ceramic multi-layer wiring board, a surface conductor layer is made of a copper-based material and an inner conductor in the ceramic multilayer is a non-copper metal having a melting point higher than a temperature at which the ceramic multilayer is fired, typically Ag. Cu and Ag form eutectic crystals when firing the surface conductor layer of Cu. This can be prevented by connecting the surface conductor layer and the inner conductor with Ag-Pd or a metal which is different from the materials of the surface wiring layer and the inner conductor and which does not form eutectic crystals with the material of the surface wiring layer at the temperature at which the surface wiring layer is fired.Type: GrantFiled: January 21, 1994Date of Patent: August 8, 1995Assignee: Nippondenso Co., Ltd.Inventors: Takashi Nagasaka, Yuji Ontani, Mitsuhiro Saitou