Abstract: A first switch is connected in parallel with a circuit element. A second switch is connected in series with a parallel circuit constituted by the circuit element and the first switch. The first switch and the second switch alternately perform on-off operation.

Abstract: An image rejection mixer includes a delay circuit for delaying one of first signals divided by a distribution circuit and a second signal provided to a second mixing circuit by the same delay amount d, or delaying the other one of the first signals divided by the distribution circuit and the second signal provided to a first mixing circuit by the same delay amount d.

Abstract: One inductor and another inductor are magnetically coupled to each other. A variable current source controls the current flowing in the one inductor. By controlling the current flowing in the one inductor, the inductance value of the other inductor is made variable.

Abstract: A first pulse selector outputs an output signal of a variable frequency divider to phase frequency detectors in a time division manner. A second pulse selector outputs a reference signal from a reference signal source to the phase frequency detectors in a time division manner. Outputs of the phase frequency detectors are provided, respectively, for multiple disposed charge pump circuits.

Abstract: A mixer includes: a VGA (12) configured to amplify one of divided two portions of an input signal at a gain of cos ?; a VGA (13) configured to amplify another one of the divided two portions of the input signal at a gain of sin ?; an IQ generator (15) configured to input an LO wave, and output an LO wave in phase with the input LO wave and an LO wave having a phase difference of 90° with respect to the input LO wave; a mixer (16) configured to input the signal output from the VGA (12) and the LO wave which is output from the IQ generator (15) , to output an RF signal; a second mixer (17) configured to input the signal from the VGA (13) and the LO wave which is output from the IQ generator, to output an RF signal; and a combiner (18).

Abstract: A first transistor (2a), a second transistor (2b), a third transistor (2c) and a fourth transistor (2d) are provided. A first transistor (2a) amplifies a first I signal VIP inputted from a first input terminal (1a). A second transistor (2b) amplifies a first Q signal VQP inputted from a second input terminal (1b). A third transistor (2c) amplifies a second I signal VIN when the second I signal VIN is inputted from a third input terminal (1c), the second I signal VIN forming a differential signal with the first I signal VIP. A fourth transistor (2d) amplifies a second Q signal VQN when the second Q signal VQN is inputted from a fourth input terminal (1d), the second Q signal VQN forming a differential signal with the first Q signal VQP.

Abstract: A local oscillator of the present invention includes: a frequency generator for outputting first and second sinusoidal signals having the same frequency but mutually different phases; a phase detector for outputting either a positive or a negative voltage depending on whether a phase difference between the first and second sinusoidal signals output from the frequency generator is greater than a reference phase difference; and a comparator for outputting a comparison result between a voltage output from the phase detector and a reference voltage, or a comparison result between the voltage output from the phase detector and a voltage obtained by inverting the polarity of the voltage, in which the frequency generator controls the phase of the first sinusoidal signal so that the phase difference approaches the reference phase difference by using the comparison result output from the comparator, enabling generating IQ signals having higher phase accuracy than conventional local oscillators.

Abstract: A circuit includes: a first line (11) in which one end thereof (11a) is coupled to a first signal input terminal (la); a second line (12) in which one end thereof (12a) is grounded and the other end thereof (12b) is coupled to a first signal output terminal (4a), the second line (12) being electromagnetically coupled to the first line (11); a third line (13) in which one end thereof (13a) is open, the third line (13) being electromagnetically coupled to the second line (12); a fourth line (21) in which one end thereof (21a) is coupled to the other end (11b) of the first line (11) and the other end thereof (21b) is open; a fifth line (22) in which one end thereof (22a) is coupled to a second signal output terminal (4b) and the other end thereof (22b) is grounded, the fifth line (22) being electromagnetically coupled to the fourth line (21); and a sixth line (23) in which one end thereof (23a) is coupled to the other end (13b) of the third line (13) and the other end thereof (23b) is coupled to a second signal

Abstract: A lock detector (8) detects an unlocked state from an output of a phase frequency comparator (1). A counter (9) counts a reference signal, in a case where an unlocked state is detected by the lock detector (8). A parameter controlling circuit (10) acquires the count value of the counter (9), and controls switching on and off of a switch (12) for a D/A converter (11) that generates a signal to be added to an output of a loop filter (3), and the output voltage of the D/A converter (11) so that the count value of the counter (9) falls within a set value.

Abstract: A first balanced/unbalanced circuit is provided that splits a first mixed wave outputted from an even harmonic mixer into first and second split signals, outputs the first split signal that is in phase with the first mixed wave to a first output terminal, and outputs the second split signal that is opposite in phase to the first mixed wave to a second output terminal. Further, a second balanced/unbalanced circuit is provided that splits a second mixed wave outputted from the even harmonic mixer into third and fourth split signals, outputs the third split signal that is in phase with the second mixed wave to the second output terminal, and outputs the fourth split signal that is opposite in phase to the second mixed wave to the first output terminal.

Abstract: A phase-frequency comparator compares a reference signal with an output signal from a variable frequency divider, and outputs an up signal of frequency and a down signal of frequency depending on results of the comparison. An AND circuit performs an AND operation between the up signal and the down signal, and outputs a result of the operation as a retiming si al CLKretime. A flip-flop circuit holds an output signal from a frequency control circuit at timing of the output signal from the AND circuit, and outputs the held output signal. At ?? modulator determines a division ratio for the variable frequency divider on the basis of the output from the flip-flop circuit.

Abstract: There is provided a polyphase filter (5) that generates first differential signals from first signals amplified by a first transistor (2-1), outputs the first differential signals from a first output terminal (5-1) and a third output terminal (5-3), generates second differential signals from second signals amplified by a second transistor (2-2), and outputs the second differential signals from the first output terminal (5-1) and the third output terminal (5-3).

Abstract: A first transistor (2a), a second transistor (2b), a third transistor (2c) and a fourth transistor (2d) are provided. A first transistor (2a) amplifies a first I signal VIP inputted from a first input terminal (1a). A second transistor (2b) amplifies a first Q signal VQP inputted from a second input terminal (1b). A third transistor (2c) amplifies a second I signal VIN when the second I signal VIN is inputted from a third input terminal (1c), the second I signal VIN forming a differential signal with the first I signal VIP. A fourth transistor (2d) amplifies a second Q signal VQN when the second Q signal VQN is inputted from a fourth input terminal (1d), the second Q signal VQN forming a differential signal with the first Q signal VQP.

Abstract: A first frequency accumulator (7a) operates using an output signal of a variable frequency divider (3) as a clock. A second frequency accumulator (7b) operates using a reference signal from a reference signal source (1) as a clock. A comparison operating circuit (11) compares the output values of the first frequency accumulator (7a) and the second frequency accumulator (7b), and calculates a parameter so that a result of the comparison falls within a set value. A digital-analog converter (9) outputs a signal to be added to an output of a loop filter (6) depending on the parameter output from the comparison operating circuit (11).

Abstract: A first frequency accumulator (7a) operates using an output signal of a variable frequency divider (3) as a clock. A second frequency accumulator (7b) operates using a reference signal from a reference signal source (1) as a clock. A comparison operating circuit (11) compares the output values of the first frequency accumulator (7a) and the second frequency accumulator (7b), and calculates a parameter so that a result of the comparison falls within a set value. A digital-analog converter (9) outputs a signal to be added to an output of a loop filter (6) depending on the parameter output from the comparison operating circuit (11).

Abstract: A lock detector (8) detects an unlocked state from an output of a phase frequency comparator (1). A counter (9) counts a reference signal, in a case where an unlocked state is detected by the lock detector (8). A parameter controlling circuit (10) acquires the count value of the counter (9), and controls switching on and off of a switch (12) for a D/A converter (11) that generates a signal to be added to an output of a loop filter (3), and the output voltage of the D/A converter (11) so that the count value of the counter (9) falls within a set value.

Abstract: A microwave amplifier including: a bias circuit that includes a line having an electrical length of one quarter the wavelength at the frequency configured to be amplified by the microwave amplifier and being connected between the output terminal of an amplifier and a bias voltage source, and a capacitor connected between a terminal where the line is connected to the bias voltage source and a ground that defines the reference potential of the microwave amplifier; and a resonant circuit that includes a resistor and a capacitor connected in series between the ground and the terminal where the line is connected to the bias voltage source.

Abstract: A microwave amplifier including: a bias circuit that includes a line having an electrical length of one quarter the wavelength at the frequency configured to be amplified by the microwave amplifier and being connected between the output terminal of an amplifier and a bias voltage source, and a capacitor connected between a terminal where the line is connected to the bias voltage source and a ground that defines the reference potential of the microwave amplifier; and a resonant circuit that includes a resistor and a capacitor connected in series between the ground and the terminal where the line is connected to the bias voltage source.

Abstract: An array antenna apparatus in which an SN ratio is improved. Antenna elements having transmission modules, respectively, are arranged in plurality, wherein the plurality of transmission modules respectively have transmission signal generators that each output a transmission intermediate frequency signal, local oscillation signal generators that each output a local oscillation signal, and transmission mixers that each mix the transmission intermediate frequency signal and the local oscillation signal with each other, thereby to carry out frequency conversion to a transmission high frequency signal. A reference signal source inputs a reference signal to the transmission signal generators and the local oscillation signal generators. The transmission intermediate frequency signal and the local oscillation signal are synchronized with each other by the reference signal.

Abstract: A transmission module including a power supply voltage control unit that sets a power supply voltage to the high frequency amplifier in a variable manner, and a control circuit that controls an amplitude control unit, a phase control unit and the power supply voltage control unit. The control circuit and the power supply voltage control unit control the power supply voltage in accordance with an output power of the high frequency amplifier. The transmission module can carry out not only phase control but also amplitude control in a continuous manner, while suppressing amplitude and phase variation, and a high frequency amplifier in the transmission module is made highly efficient. In addition, a large directional gain, a low side lobe level and a low power consumption are achieved, as a phased array antenna apparatus using a transmission module.