Abstract: A semiconductor device has an IC chip with a thickness of equal to or less than 100 ?m and includes a semiconductor substrate. A device forming region is within the depth of approximately equal to or less than 5 ?m from a surface of the semiconductor substrate, and a total thickness of the semiconductor substrate is from 5 ?m to 100 ?m. A BMD layer for carrying out gettering of metal impurities is provided immediately under the device forming region. Since a gettering site is provided immediately under the device forming region, in a device or the like of which extreme thinness is required, degradation of device characteristics and reliability due to contamination of metal impurities can be prevented, and stabilize and improve the device yield.

Abstract: A semiconductor device has an IC chip with a thickness of equal to or less than 100 ?m and includes a semiconductor substrate. A device forming region is within the depth of approximately equal to or less than 5 ?m from a surface of the semiconductor substrate, and a total thickness of the semiconductor substrate is from 5 ?m to 100 ?m. A BMD layer for carrying out gettering of metal impurities is provided immediately under the device forming region. Since a gettering site is provided immediately under the device forming region, in a device or the like of which extreme thinness is required, degradation of device characteristics and reliability due to contamination of metal impurities can be prevented, and stabilize and improve the device yield.

Abstract: A method for manufacturing a semiconductor device comprising a first conductivity type semiconductor substrate, a memory cell region and a peripheral circuit region formed on the substrate, the memory cell region and the peripheral circuit region having a plurality of second conductivity type transistors (Tr's), which comprises the steps of:(i-a) forming source/drain regions in a memory cell formation region (MCFR) on the substrate by implanting a second conductivity type impurity, (ii-a) forming a gate insulating film and gate electrodes on the MCFG and a peripheral circuit formation region (PCFR) of the substrate, thereby providing the plurality of second conductivity type Tr's in the MCFG, (iii-a) implanting a first conductivity type impurity into the entire surface of the substrate with the gate electrodes used as a mask to form a device isolation region in the MCFG and, at the same time, to allow the first conductivity type impurity to be contained to a predetermined depth in a second conductivity type T