Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: In an input cell policing method in a network of an asynchronous transfer mode, according to information contained in a header field of each input cell, a group to which the cell belongs is identified. For each group, there are set a plurality of time frames having a predetermined length and mutually different phases to count the number of input cells in each time frame period. For each time frame, the count value of input cells is compared with a predetermined threshold value. An input cell for which the count value exceeds the threshold value in either one of the time frames is assumed to be an excess cell. The excess cell is discarded or a violation mark is added thereto.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.

Abstract: A game signal conversion apparatus includes a CPU which generates image data representing a plurality of kinds of gradations or color tones similar to gradations or color tones utilized in display game characters in a first game machine on the basis of image display data stored in a ROM contained in a cartridge for first game machine. The image data processed by the CPU is transferred to a second game machine in a manner that the image data is in conformity with a format and a timing for controlling display in the second game machine. Furthermore, commands by which necessary data are inputted in converting various kinds of data for the first game machine into various kinds of data for the second game machine are represented by illustrations or symbols (command characters), so that the necessary data can be inputted through selection of the symbols.

Abstract: A semiconductor memory device has a plurality of divided memory blocks, each of which has its X-system addresses assigned so that an equal number of word lines in a plurality of sets of memory mats and sense amplifiers may be selected. Each memory block is equipped with a plurality of internal voltage drop circuits for generating a supply voltage from the outside into the operating voltages of the sense amplifiers.

Abstract: A dynamic type RAM is provided wherein the level of a precharge control signal supplied to a gate of a precharge MOSFET to precharge complementary data lines to a half level is made the half level during a period from the memory access until the selection of the word line, at the latest. Also, the precharge control signal, corresponding to a memory mat selected according to establishing of an address, is set to a low level, while the precharge control signal corresponding to a non-selective memory mat is set to a high level.