Abstract: In a nonvolatile memory device provided in a semiconductor device, when data is erased based on a band-to-band tunneling scheme, supply of a boosted voltage to a memory cell (MC) to be erased is ended when a condition that an output voltage (VUCP) of a charge pump circuit has recovered to a predetermined reference voltage is satisfied and additionally a condition that a predetermined reference time has elapsed since start of supply of the boosted voltage (VUCP) to the memory cell (MC) to be erased is satisfied.

Abstract: In a nonvolatile memory device (4) provided in a semiconductor device, when data is erased based on a band-to-band tunneling scheme, supply of a boosted voltage to a memory cell (MC) to be erased is ended when a condition that an output voltage (VUCP) of a charge pump circuit (52) has recovered to a predetermined reference voltage is satisfied and additionally a condition that a predetermined reference time has elapsed since start of supply of the boosted voltage (VUCP) to the memory cell (MC) to be erased is satisfied.

Abstract: In a nonvolatile memory device (4) provided in a semiconductor device, when data is erased based on a band-to-band tunneling scheme, supply of a boosted voltage to a memory cell (MC) to be erased is ended when a condition that an output voltage (VUCP) of a charge pump circuit (52) has recovered to a predetermined reference voltage is satisfied and additionally a condition that a predetermined reference time has elapsed since start of supply of the boosted voltage (VUCP) to the memory cell (MC) to be erased is satisfied.

Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.

Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.

Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.

Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.

Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.

Abstract: A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.

Abstract: An operation of erasing data in a memory block of a nonvolatile semiconductor memory device employs an operation of collectively applying an erase pulse to the memory block, and an operation of collectively applying an erase pulse to a limited region in the memory block. Thereby, the number of the erase pulses excessively applied to the memory cells, which passed verify, can be reduced as compared with a conventional structure so that the number of the memory cells to be subjected to over-erase recovery write decreases, and the total block erase time can be short.

Abstract: In a memory block that is to be subjected to an erasure operation, voltage of the ground level is selectively supplied to only one word line. By applying an erasure pulse to a source line, memory cell transistors have their threshold voltages shifted. As to another word line, a pulse of a positive voltage is supplied in synchronization to the application of an erasure pulse to the source line. Another group of memory cell transistors do not have their threshold voltages shifted.

Abstract: An operation of erasing data in a memory block of a nonvolatile semiconductor memory device employs an operation of collectively applying an erase pulse to the memory block, and an operation of collectively applying an erase pulse to a limited region in the memory block. Thereby, the number of the erase pulses excessively applied to the memory cells, which passed verify, can be reduced as compared with. a conventional structure so that the number of the memory cells to be subjected to over-erase recovery write decreases, and the total block erase time can be short.

Abstract: It is an object to obtain a nonvolatile semiconductor storage device and a data erasing method thereof in which a time required for a data erasing operation can be shortened. When second and succeeding erasing commands are input at a step SP101, a final voltage value of a batch writing pulse in a last data erasing operation is read from a storage portion (2a) at a step SP102. At a step SP103, next, a control portion (2) sets a starting voltage value of a batch writing pulse in a present data erasing operation based on the final voltage value of the batch writing pulse in the last data erasing operation. For example, in the case in which the final voltage value of the batch writing pulse in the last data erasing operation is VWL=8.00 V and VWell=VSL=−6.00 V, the starting voltage value of the batch writing pulse is currently set to VWL=7.75 V and VWell=VSL=−5.75 V with a reduction of one step.

Abstract: It is an object to obtain a nonvolatile semiconductor storage device and a data erasing method thereof in which a time required for a data erasing operation can be shortened. When second and succeeding erasing commands are input at a step SP101, a final voltage value of a batch writing pulse in a last data erasing operation is read from a storage portion (2a) at a step SP102. At a step SP103, next, a control portion (2) sets a starting voltage value of a batch writing pulse in a present data erasing operation based on the final voltage value of the batch writing pulse in the last data erasing operation. For example, in the case in which the final voltage value of the batch writing pulse in the last data erasing operation is VWL=8.00 V and VWell=VSL=−6.00 V, the starting voltage value of the batch writing pulse is currently set to VWL=7.75 V and VWell=VSL=−5.75 V with a reduction of one step.

Abstract: In a memory block that is to be subjected to an erasure operation, voltage of the ground level is selectively supplied to only one word line. By applying an erasure pulse to a source line, memory cell transistors have their threshold voltages shifted. As to another word line, a pulse of a positive voltage is supplied in synchronization to the application of an erasure pulse to the source line. Another group of memory cell transistors do not have their threshold voltages shifted.

Abstract: Erasing is performed two times for narrowing a distribution width of threshold voltages of memory cells, and reducing the number of memory transistors to be subjected to over-erase verify. The erase verify voltage for the first erasing is set more strictly than the erase verify voltage for the second erasing. The erase pulses for the second erasing can be reduced in number, and the erasing time can be further reduced.

Abstract: Erasing is performed two times for narrowing a distribution width of threshold voltages of memory cells, and reducing the number of memory transistors to be subjected to over-erase verify. The erase verify voltage for the first erasing is set more strictly than the erase verify voltage for the second erasing. The erase pulses for the second erasing can be reduced in number, and the erasing time can be further reduced.

Abstract: A flash memory and its data refresh method, where data read out in program verify mode and erase verify mode from read address are compared in each address (ST110), and data of a memory cell corresponding to inconsistent data are rewritten (ST112). Or adding values of data read out in the program verify mode and the erase verify mode are compared in each block (ST137) and a defective block is retrieved and data in each address are compared in the defective block (ST160), and data of a memory cell corresponding to inconsistent data are rewritten (ST162). Thereby, defective data can be retrieved and corrected.