Patents by Inventor Mitsuhiro Yamaga
Mitsuhiro Yamaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5247518Abstract: A high-speed ring LAN capable of accommodating at least one public network having a signal transmission rate of 155.57 MHz, and at least one sub-LAN having a signal transmission rate of 100 MHz. The high-speed LAN has a signal transmission rate of 155.52 Mbps .times.n (n is an even number). SONET (Synchronous Optical NETwork) subframes each comprising a 9 bytes .times.9 section overhead area and a 261 bytes .times.9 virtual container 4 (VC-4) area flow in a time-divisional n-multiplexed format. The respective node devices inserted in the transmission path have one or more ports to accommodate sub-LANs or public networks. Information is exchanged in units of a fixed-length packet between a received SONET subframe and an asynchronous port whereas information is exchanged in units of a byte between the SONET subframe and a synchronous port.Type: GrantFiled: January 13, 1992Date of Patent: September 21, 1993Assignee: Hitachi, Ltd.Inventors: Yoshihiro Takiyasu, Toshiki Tanaka, Taihei Suzuki, Eiichi Amada, Yukiji Yamauchi, Mitsuhiro Yamaga, Matsuaki Terada, Kunio Hiyama
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Patent number: 5224096Abstract: A frame strip method for a bridge circuit for transparently forwarding data between a plurality of LANs (Local Area Network) without frame infinite circulation. The numbers of transmission/receive frames are counted. In counting the number, the validity/invalidity of a transmission frame is judged in accordance with the kind of the transmission frame. The validity/invalidity and strip/receive of a receive frame are judged in accordance with the kind of the receive frame. In accordance with the numbers of valid transmission/receive frames, a receive frame is stripped from the transmission line if the condition of (transmission frame number)>(receive frame number) is met.Type: GrantFiled: September 17, 1990Date of Patent: June 29, 1993Assignee: Hitachi, Ltd.Inventors: Katsuyoshi Onishi, Koichi Kimura, Mitsuhiro Yamaga, Osamu Takada, Masahito Sasaki
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Patent number: 5220562Abstract: Frontend LANs connecting plural stations are connected to plural nodes of a backbone LAN respectively. The backbone LAN is constituted by plural physical or logical links, and each node corresponds to each frontend LAN. A first data block is segmented into one or plural second data block units of fixed length and transferred to destination nodes, a bridge is provided in order to assemble the second data blocks into the first data block. The bridge can transmit the second data blocks to arbitrary links, and the receiving is performed through one link. The bridge a decoder also has a decoder for decoding whether the learning should be performed or not, based on the learning indication information existing in the second data block including the routing information.Type: GrantFiled: May 8, 1990Date of Patent: June 15, 1993Assignee: Hitachi, Ltd.Inventors: Osamu Takada, Katsuyoshi Onishi, Koichi Kimura, Kazunori Nakamura, Yoshihiro Takiyasu, Mitsuhiro Yamaga, Kunio Hiyama
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Patent number: 5210748Abstract: The present invention relates to an address filter method and unit to be used in a bridge unit or the like for connecting networks. The address filter unit carries out an address filter processing between a plurality of networks by using address information extracted from an incoming information frame registered in an entry table. In order to improve the processing efficiency of the address filter processing, the address filter unit includes timers corresponding to each address information registration, timer updating means for sequentially and intermittently advancing each timer value, and means for deleting registration of the address information corresponding to the timers from the entry table when a timer value becomes equal to or above a predetermined value.Type: GrantFiled: February 4, 1991Date of Patent: May 11, 1993Assignee: Hitachi, Ltd.Inventors: Katsuyoshi Onishi, Osamu Takada, Koichi Kimura, Mitsuhiro Yamaga, Toshihiko Ogura, Yasushi Shibata
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Patent number: 5113392Abstract: In a network having a plurality of node apparatus connected to a transmission line, each node apparatus segmenting a transmission message into information blocks of a predetermined length and transmitting them to the transmission line in the form of a fixed length packet (cell) having a source address, each node apparatus sequentially stores packets having different source addresses in vacant memory blocks of a buffer memory. There is written in each memory block the packet data as well as a next address pointer indicating a memory block in which the next received packet having the same source address is stored. When a packet containing the last information block of a message is received, stored in a read address queue is the address indicating the memory block which stores the first information block of the same packet.Type: GrantFiled: June 18, 1990Date of Patent: May 12, 1992Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.Inventors: Yoshihiro Takiyasu, Mitsuhiro Yamaga, Kazunori Nakamura, Eiichi Amada, Hidehiko Jusa, Naoya Kobayashi, Osamu Takada, Satoru Hirayama, Tatsuhito Iiyama
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Patent number: 5103447Abstract: A high-speed ring LAN capable of accommodating at least one public network having a signal transmission rate of 155.57 MHz, and at least one sub-LAN having a signal transmission rate of 100 MHz. The high-speed LAN has a signal transmission rate of 155.52 Mbps.times.n (n is an even number). SONET (Synchronous Optical NETwork) subframes each comprising a 9 bytes.times.9 section overhead area and a 261 bytes.times.9 virtual container 4 (VC-4) area flow in a time-divisional n-multiplexed format. The respective node devices inserted in the transmission path have one or more ports to accommodate sub-LANs or public networks. Information is exchanged in units of a fixed-length packet between a received SONET subframe and an asynchronous packet whereas information is exchanged in units of a byte between the SONET subframe and a synchronous port.Type: GrantFiled: August 29, 1989Date of Patent: April 7, 1992Assignee: Hitachi, Ltd.Inventors: Yoshihiro Takiyasu, Toshiki Tanaka, Taihei Suzuki, Eiichi Amada, Yukiji Yamauchi, Mitsuhiro Yamaga, Matsuaki Terada, Kunio Hiyama
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Patent number: 4899142Abstract: A ring network system in which a plurality of line concentrators each having terminal stations connected thereto through respective branch lines are interconnected through at least one ring transmission lines. Each line concentrator includes configuration control switches capable of disconnecting from the ring transmission line all the branch lines placed under control of the line concentrator while holding the ring transmission line in the state to allow communication. The branch line(s) disconnected from the ring transmission line form(s) a local ring through cooperation with an internal transmission line. The line concentrator detected abnormality of communication or the line concentrator to be set to the rest state can undergo internal diagnosis operation or continue to be in the rest state without disturbing the communication among other line concentrators.Type: GrantFiled: May 4, 1987Date of Patent: February 6, 1990Assignee: Hitachi, Ltd.Inventors: Susumu Nakayashiki, Jiro Kashio, Takeshi Harakawa, Yoshinori Bekki, Mitsuhiro Yamaga
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Patent number: 4847611Abstract: In a ring communications system including a plurality of line concentrators that are connected in the form of a ring, the line concentrators are connected together via a main ring, and the terminal stations connected to the line concentrators are connected to the main ring via ring subsidiaries. The main ring and the ring subsidiaries are connected together via ring connection switches that so work as to connect or disconnect the main ring and the ring subsidiaries. The ring connection switch is so constructed as to maintain the connected condition even when the power source of the line concentrator is in the turned-off state.Type: GrantFiled: August 19, 1987Date of Patent: July 11, 1989Assignee: Hitachi, Ltd.Inventors: Yoshinori Bekki, Hiroyuki Wada, Mitsuhiro Yamaga, Susumu Nakayashiki
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Patent number: 4759015Abstract: In a network system wherein a plurality of terminal devices communicates with each other via respective node devices over a ring transmission line, a transmitting node device can confirm whether a multicast information transmission has succeeded or failed. The transmitting node device send a response frame after a multicast information frame. A receiving node device relays the multicast information frame and a response frame from the upstream node device to the downstream one when the multicast information has been received successfully, or in case of a failure in receiving the multicast information, sends a response frame to the downstream node device by changing at least part of the response frame from the upstream node device. The transmitting node device can determine from a received response frame if there is one or more of the receiving node devices which cannot receive the multicast information.Type: GrantFiled: September 26, 1986Date of Patent: July 19, 1988Assignee: Hitachi, Ltd. and Hitachi Microcomputer Eng. Ltd.Inventors: Atsushi Takai, Kazunori Nakamura, Yoshihiro Takiyasu, Nagatoshi Usami, Mitsuhiro Yamaga
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Patent number: 4675884Abstract: A decoding circuit is operative to decode a differential Manchester code consisting of four symbols "J", "K", "1" and "0" each composed of two consecutive signal elements. For detection of the symbol "J" and consequent determination of the symbol boundary, the decoding circuit has a circuit configuration which takes advantage of the fact that the symbol "K" immediately follows the symbol "J" and three consecutive signal elements, two of which are included in the symbol "J" and one of which is for a symbol immediately preceding the symbol "J", have the same polarity. To prevent an error that a second occurrence of the symbol "J" is detected after completion of detection of the symbol "J", the decoding circuit has an additional circuit configuration which inhibits the detection of the symbol "J" until the symbol "0" or the symbol "1", for example, is detected.Type: GrantFiled: December 23, 1985Date of Patent: June 23, 1987Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.Inventors: Kazunori Nakamura, Mitsuhiro Yamaga, Ryozo Yoshino, Norihiko Sugimoto