Abstract: A semiconductor device includes a substrate; a first semiconductor layer above the substrate, a second semiconductor layer between the substrate and the first semiconductor layer, first and second conductors, an electrode, and first and second insulating films. The first and second semiconductor layers have a first end and a second end opposite to the first end. The first conductor is connected to the first ends of the first and second semiconductor layers. The second conductor includes a first portion connected to the second ends of the first and second semiconductor layers and a second portion positioned inside the substrate. The electrode faces portions of first and second semiconductor layers between the first end and the second end thereof. The first insulating film is provided between the first semiconductor layer and the electrode; and the second insulating film is provided between the second semiconductor layer and the electrode.

Abstract: A semiconductor device includes a substrate; a first semiconductor layer above the substrate, a second semiconductor layer between the substrate and the first semiconductor layer, first and second conductors, an electrode, and first and second insulating films. The first and second semiconductor layers have a first end and a second end opposite to the first end. The first conductor is connected to the first ends of the first and second semiconductor layers. The second conductor includes a first portion connected to the second ends of the first and second semiconductor layers and a second portion positioned inside the substrate. The electrode faces portions of first and second semiconductor layers between the first end and the second end thereof. The first insulating film is provided between the first semiconductor layer and the electrode; and the second insulating film is provided between the second semiconductor layer and the electrode.

Abstract: The ESD protection circuit includes a detection controlling circuit that is connected between the power supply line and the grounding line, detects a current flowing through the power supply line and outputs a controlling signal responsive to a result of the detection. The ESD protection circuit includes a protecting nMOS transistor connected to the power supply line at a drain thereof and receives the controlling signal at a gate thereof. The ESD protection circuit includes one stage of PN-junction diode connected to a source of the protecting nMOS transistor at an anode thereof and to the grounding line at a cathode thereof.

Abstract: A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an optical proximity effect, for edges (first edges) meeting a condition among the edges constituting a designed pattern. Subsequently, The second correction is executed for an edge (second edge) which does not meet the condition, by use of the correction value of any one of the edges (first edges) adjacent to the second edge among the first edges for which the first correction is executed, thus connecting the corrected first edge and the corrected second edge by a line segment. The pattern is corrected to a shape suitable for a mask drawing and a check with simple processing.

Abstract: A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an optical proximity effect, for edges (first edges) meeting a condition among the edges constituting a designed pattern. Subsequently, The second correction is executed for an edge (second edge) which does not meet the condition, by use of the correction value of any one of the edges (first edges) adjacent to the second edge among the first edges for which the first correction is executed, thus connecting the corrected first edge and the corrected second edge by a line segment. The pattern is corrected to a shape suitable for a mask drawing and a check with simple processing.

Abstract: A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an optical proximity effect, for edges (first edges) meeting a condition among the edges constituting a designed pattern. Subsequently, The second correction is executed for an edge (second edge) which does not meet the condition, by use of the correction value of any one of the edges (first edges) adjacent to the second edge among the first edges for which the first correction is executed, thus connecting the corrected first edge and the corrected second edge by a line segment. The pattern is corrected to a shape suitable for a mask drawing and a check with simple processing.

Abstract: A chip division information storage unit configured to register chip division information; a chip layout generation unit configured to generate master mask chip layout information by sequentially allotting sub-patterns to a master mask in an order beginning with the largest from the plurality of sub-patterns; a master mask chip layout information storage unit configured to register the master mask chip layout information; a chip pattern data generation unit configured to generate master mask chip pattern data by referencing the reticle chip pattern data and divide each chip in accordance with the master mask chip layout data; a master mask pattern data information storage unit configured to register the master mask chip pattern data; and a pattern data generation unit configured to generate master mask pattern data by referencing the master mask chip layout information and the master mask chip pattern data, are provided.

Abstract: A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an optical proximity effect, for edges (first edges) meeting a condition among the edges constituting a designed pattern. Subsequently, The second correction is executed for an edge (second edge) which does not meet the condition, by use of the correction value of any one of the edges (first edges) adjacent to the second edge among the first edges for which the first correction is executed, thus connecting the corrected first edge and the corrected second edge by a line segment. The pattern is corrected to a shape suitable for a mask drawing and a check with simple processing.

Abstract: A chip division information storage unit configured to register chip division information; a chip layout generation unit configured to generate master mask chip layout information by sequentially allotting sub-patterns to a master mask in an order beginning with the largest from the plurality of sub-patterns; a master mask chip layout information storage unit configured to register the master mask chip layout information; a chip pattern data generation unit configured to generate master mask chip pattern data by referencing the reticle chip pattern data and divide each chip in accordance with the master mask chip layout data; a master mask pattern data information storage unit configured to register the master mask chip pattern data; and a pattern data generation unit configured to generate master mask pattern data by referencing the master mask chip layout information and the master mask chip pattern data, are provided.

Abstract: There is disclosed a semiconductor device having an MOS gate for reducing variations in threshold voltage (V.sub.th) with time wherein a surface protective film is not formed in a device area including channels but only in a device peripheral area, thereby reducing the amount of hydrogen atoms migrating to a silicon-silicon oxide interface in a cell area and, accordingly, reducing the number of Si--H chemical bonds at the interface.

Abstract: An n.sup.+ semiconductor substrate (1) using a silicon wafer as a base material and including As includes oxygen of which the concentration is in the range of 12E17 atoms/cm.sup.3 to 20E17 atoms/cm.sup.3. The first epitaxial growth layer (2) of n type and a diffusion layer (3) of p type are formed in sequence on the second major surface (1S2) of the semiconductor substrate (1). The thickness of an epitaxial a growth layer (10) is set to be not more than 20 .mu.m. A trench (6) is formed so as to extend from a surface of the diffusion layer (3) to the inside of the first epitaxial growth layer (2). A gate oxide film (5) is formed on a bottom surface (6B) and a wall surface (6W) of the trench (6) and a conductive layer (11) fills the trench (6). An n-type source layer (4) is formed at a corner (6C) of the trench (6). After that, predetermined electrodes are formed and so on, to complete a device.

Abstract: The present invention provides a laser device comprising a substrate; an active layer; a multi-quantum-well layer disposed on one side of the active layer and optically coupled therewith; a diffraction grating layer disposed on a side of the active layer and optically coupled therewith; and a device for applying a reverse voltage to the multi-quantum-well layer. The laser device can generate a light output, with its wavelength being controlled electrically for a 350 .ANG. range at a 1.55 .mu.m wavelength.

Abstract: A semiconductor light-emitting device fabricated as a double hetero-structure InGaAsP/InP-type laser. The laser includes a buffer layer made of a semiconductor. The buffer layer is located at the upper edge of the flow region of electrons as seen from the active layer. The conductivity type of the buffer layer is opposite to that of a clad layer located at the upper edge of the flow region of electrons seen from the buffer layer. A, the band gap of the buffer layer is wider than that of the active layer but narrower than that of a clad layer adjacent to the buffer layer. The thickness of the buffer layer does not exceed the diffusion length of the electrons injected into the buffer layer.

Abstract: In a semiconductor light emitting device, a buried layer of a semiconductor is selectively formed in at least one of a first and a second clad layers in order to determine a light emitting region by the configuration of the buried layer of the semiconductor. The buried layer of the semiconductor has a conductivity type which is opposite to the conductivity type of the surrounding clad layer and an index of refraction which is different from the index of refraction of the surrounding clad layer.

Abstract: There is disclosed a semiconductor device having an MOS gate for reducing variations in threshold voltage (Vth) with time wherein a surface protective film is not formed in a device area including channels but only in a device peripheral area, thereby reducing the amount of hydrogen atoms migrating to a silicon-silicon oxide interface in a cell area and, accordingly, reducing the number of Si—H chemical bonds at the interface.