Abstract: An image processing apparatus of the disclosure includes: a blocking unit configured to divide image information into blocks; a map information acquisition unit configured to acquire at least one piece of map information in which pieces of reference pixel information and pieces of positional information are associated with a target pixel in each of the blocks, the pieces of reference pixel information denoting at least one reference pixel referenced by the target pixel, each of the pieces of positional information denoting a positional relationship between the target pixel and the at least one reference pixel; and a reference pixel information selecting unit configured to select one piece of reference pixel information of the pieces of reference pixel information included in the at least one piece of map information based on a pixel value of the target pixel and a pixel value of the at least one reference pixel.

Abstract: A display device includes: a deterioration amount increment calculation unit that calculates an increment of a deterioration amount of an organic light-emitting element included in each of pixels, based on gradation data included in image data; a deterioration amount accumulation unit that accumulates, every fixed time, the increment of the deterioration amount calculated by the deterioration amount increment calculation unit; and a correction unit that corrects luminance of the pixel based on a total amount of increments of the deterioration amount accumulated by the deterioration amount accumulation unit.

Abstract: A display device includes: a deterioration amount increment calculation unit that calculates an increment of a deterioration amount of an organic light-emitting element included in each of pixels, based on gradation data included in image data; a deterioration amount accumulation unit that accumulates, every fixed time, the increment of the deterioration amount calculated by the deterioration amount increment calculation unit; and a correction unit that corrects luminance of the pixel based on a total amount of increments of the deterioration amount accumulated by the deterioration amount accumulation unit.

Abstract: A coding device has a difference calculating unit that calculates a quantized value, which is represented by lower-order bits than a quantization bit rate allocated to a processing unit in image data in a selected coding pattern, from a quantized value obtained by quantizing a pixel value in the processing unit with a maximum quantization bit rate in the coding device, as a difference.

Abstract: An image processing apparatus of the disclosure includes: a blocking unit configured to divide image information into blocks; a map information acquisition unit configured to acquire at least one piece of map information in which pieces of reference pixel information and pieces of positional information are associated with a target pixel in each of the blocks, the pieces of reference pixel information denoting at least one reference pixel referenced by the target pixel, each of the pieces of positional information denoting a positional relationship between the target pixel and the at least one reference pixel; and a reference pixel information selecting unit configured to select one piece of reference pixel information of the pieces of reference pixel information included in the at least one piece of map information based on a pixel value of the target pixel and a pixel value of the at least one reference pixel.

Abstract: The present invention provides an image encoding device that can balance encoding at a high compression ratio and restoration of a high-quality image by decoding in a short processing time. Compression mode determination means 3 determines a compression mode to be one of DPCM and PCM based on target pixel data inputted from a terminal 21 and predicted data calculated by a predetermined method. For the DPCM, DPCM compression means 5 compresses a difference value between the target pixel data and the predicted data to DPCM encoded data having a predetermined DPCM code length. For the PCM, PCM compression means 7 compresses the target pixel data to PCM encoded data having a PCM code length determined by PCM code length determination means 9. The PCM code length determination means 9 calculates the PCM code length for each piece of target pixel data such that a total of post-encoding code lengths becomes an allowable value or less in a unit of predetermined pixel group among the plurality of pixels.

Abstract: The present invention provides an image encoding device that can balance encoding at a high compression ratio and restoration of a high-quality image by decoding in a short processing time. Compression mode determination means 3 determines a compression mode to be one of DPCM and PCM based on target pixel data inputted from a terminal 21 and predicted data calculated by a predetermined method. For the DPCM, DPCM compression means 5 compresses a difference value between the target pixel data and the predicted data to DPCM encoded data having a predetermined DPCM code length. For the PCM, PCM compression means 7 compresses the target pixel data to PCM encoded data having a PCM code length determined by PCM code length determination means 9. The PCM code length determination means 9 calculates the PCM code length for each piece of target pixel data such that a total of post-encoding code lengths becomes an allowable value or less in a unit of predetermined pixel group among the plurality of pixels.

Abstract: A light source device which is used as the backlight device and does not generate sound is provided. One or more flat substrates each having a light emitting element on its surface side are supported by a chassis having a conductive flat plate surface so that back surfaces of the substrates are opposed to the flat plate surface. The substrate comprises first wiring conductive thin films on a surface side of an insulation substrate, and one or more second radiating or wiring conductive thin films on a back surface side of the insulation substrate. Two terminals of the light emitting element are connected to the two adjacent first conductive thin films. A potential of at least one of the second conductive thin films is fixed to have a constant potential difference or preferably fixed to the same potential with respect to that of the flat plate surface of the chassis.

Abstract: A light source device which is used as the backlight device and does not generate sound is provided. One or more flat substrates each having a light emitting element on its surface side are supported by a chassis having a conductive flat plate surface so that back surfaces of the substrates are opposed to the flat plate surface. The substrate comprises first wiring conductive thin films on a surface side of an insulation substrate, and one or more second radiating or wiring conductive thin films on a back surface side of the insulation substrate. Two terminals of the light emitting element are connected to the two adjacent first conductive thin films. A potential of at least one of the second conductive thin films is fixed to have a constant potential difference or preferably fixed to the same potential with respect to that of the flat plate surface of the chassis.

Abstract: A high level synthesis device includes a high level synthesis section and a cycle accurate model. The high level synthesis section may perform high level synthesis of hardware including a plurality of components and a controller for controlling the plurality of components. The cycle accurate model may be configured to verify a state of at least one of the plurality of components and the controller at a cycle accurate level, with a general-purpose programming language.

Abstract: A debug device has a serialization section for converting a parallel program to a serial program and creating debug data indicating the corresponding relation between the parallel program and the serial program. The debug device further has a storage section for storing the debug data and a conversion section for mutually converting the corresponding data between the parallel program and the serial program based on the debug data in order for an operator to efficiently perform a debug operation.

Abstract: A high level synthesis device includes a high level synthesis section for performing high level synthesis of hardware including a plurality of components and a controller for controlling the plurality of components; and a cycle accurate model generation section for generating a cycle accurate model, capable of verifying a state of at least one of the plurality of components and the controller at a cycle accurate level, with a general-purpose programming language.

Abstract: A high-level synthesis apparatus for synthesizing a register transfer level logic circuit from a behavioral description describing a processing operation of the circuit, comprises a low power consumption circuit generation section for generating a low power consumption circuit which stops or inhibits circuit operations of partial circuits constituting the logic circuit only when the partial circuits are in a wait state, so to achieve low power consumption. The low power consumption circuit generation section is synthesized along with the logic circuit.

Abstract: A debug device has a serialization section for converting a parallel program to a serial program and creating debug data indicating the corresponding relation between the parallel program and the serial program. The debug device further has a storage section for storing the debug data and a conversion section for mutually converting the corresponding data between the parallel program and the serial program based on the debug data in order for an operator to efficiently perform a debug operation.

Abstract: A high-level synthesis method is provided for synthesizing a register transfer level logic circuit based on a behavioral description in which processing behaviors are described. The method includes the steps of extracting information on a bus connection resource from the behavioral description, storing the information on the bus connection resource in a bus connection resource database, referencing the bus connection resource database, referencing a bus protocol library having a preloaded bus protocol, and automatically generating a target interface circuit based on a result of each of the bus connection resource database referencing step and the bus protocol library referencing step.

Abstract: A high-level synthesis apparatus for synthesizing a register transfer level logic circuit from a behavioral description describing a processing operation of the circuit, comprises a low power consumption circuit generation section for generating a low power consumption circuit which stops or inhibits circuit operations of partial circuits constituting the logic circuit only when the partial circuits are in a wait state, so to achieve low power consumption. The low power consumption circuit generation section is synthesized along with the logic circuit.

Abstract: A high-level synthesis method is provided for synthesizing a register transfer level logic circuit based on a behavioral description in which processing behaviors are described. The method includes the steps of extracting information on a bus connection resource from the behavioral description, storing the information on the bus connection resource in a bus connection resource database, referencing the bus connection resource database, referencing a bus protocol library having a preloaded bus protocol, and automatically generating a target interface circuit based on a result of each of the bus connection resource database referencing step and the bus protocol library referencing step.

Abstract: A system for detecting power consumption of an integrated circuit obtains a frequency of data holding operations, unreferred data storing operations, and unupdated data storing operations with a data holding operation frequency calculating section, an unreferred data storing operation frequency calculating section, and an unupdated data storing operation frequency calculating section based on the number of times of a signal transition from connection information of the integrated circuit and control conditions when data is referred to registers, and obtains power consumption caused by each of the operations from the number of times of the signal transition, a load capacity, and an operation voltage.